Inventor · disambiguated record
Elliot N. Tan
Also filed as: TAN ELLIOT · TAN ELLIOT N
34 granted patents·16 pending applications·94 citations·filing 2004–2024
96Inventor score
Top patents by PatentIndex Score
50 records- 0196US10892223B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2016·Granted Jan 12, 2021·11 cites·25 claims
- 0295US12218052B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2023·Granted Feb 4, 2025·1 cites·20 claims
- 0394US12148734B2Transistors, memory cells, and arrangements thereofINTEL CORP·Filed 2020·Granted Nov 19, 2024·3 cites·20 claims
- 0494US11056492B1Dense memory arrays utilizing access transistors with back-side contactsINTEL CORP·Filed 2019·Granted Jul 6, 2021·9 cites·18 claims
- 0594US10211088B2Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnectsINTEL CORP·Filed 2015·Granted Feb 19, 2019·11 cites·20 claims
- 0693US10409152B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2017·Granted Sep 10, 2019·4 cites·20 claims
- 0793US9793159B2Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2013·Granted Oct 17, 2017·13 cites·18 claims
- 0892US11888043B2Contact over active gate structures with conductive gate taps for advanced integrated circuit structure fabricationINTEL CORP·Filed 2023·Granted Jan 30, 2024·1 cites·20 claims
- 0991US11854787B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2022·Granted Dec 26, 2023·1 cites·19 claims
- 1091US11139300B2Three-dimensional memory arrays with layer selector transistorsINTEL CORP·Filed 2019·Granted Oct 5, 2021·5 cites·20 claims
- 1188US9558947B2Pattern decomposition lithography techniquesWALLACE CHARLES H·Filed 2011·Granted Jan 31, 2017·6 cites·16 claims
- 1288US2025125260A1Advanced lithography and self-assembled devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 1387US10490519B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2017·Granted Nov 26, 2019·2 cites·20 claims
- 1485US11373950B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2020·Granted Jun 28, 2022·1 cites·19 claims
- 1585US11107786B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2019·Granted Aug 31, 2021·2 cites·20 claims
- 1683US10204830B2Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2017·Granted Feb 12, 2019·3 cites·20 claims
- 1780US8314034B2Feature size reductionTAN ELLIOT N·Filed 2010·Granted Nov 20, 2012·7 cites·20 claims
- 1880US2024389300A1Three-dimensional memory arrays with layer selector transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 1979US11189614B2Process etch with reduced loading effectINTEL CORP·Filed 2018·Granted Nov 30, 2021·2 cites·15 claims
- 2077US9379010B2Methods for forming interconnect layers having tight pitch interconnect structuresINTEL CORP·Filed 2014·Granted Jun 28, 2016·4 cites·22 claims
- 2176US12278204B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2021·Granted Apr 15, 2025·0 cites·15 claims
- 2275US2024120397A1Contact over active gate structures with conductive gate taps for advanced integrated circuit structure fabricationINTEL CORP·Filed 2023·Application pending·0 cites
- 2374US8860184B2Spacer assisted pitch division lithographySIVAKUMAR SWAMINATHAN·Filed 2011·Granted Oct 14, 2014·4 cites·20 claims
- 2473US12249541B2Vertical edge blocking (VEB) technique for increasing patterning process marginINTEL CORP·Filed 2023·Granted Mar 11, 2025·0 cites·7 claims
- 2572US12114479B2Three-dimensional memory arrays with layer selector transistorsINTEL CORP·Filed 2021·Granted Oct 8, 2024·0 cites·20 claims
- 2669US9659860B2Method and structure to contact tight pitch conductive layers with guided viasINTEL CORP·Filed 2013·Granted May 23, 2017·2 cites·20 claims
- 2764US7977248B2Double patterning with single hard maskINTEL CORP·Filed 2007·Granted Jul 12, 2011·2 cites·20 claims
- 2858US11581412B2Contact over active gate structures with conductive gate taps for advanced integrated circuit structure fabricationINTEL CORP·Filed 2019·Granted Feb 14, 2023·0 cites·22 claims
- 2957US11594448B2Vertical edge blocking (VEB) technique for increasing patterning process marginINTEL CORP·Filed 2019·Granted Feb 28, 2023·0 cites·18 claims
- 3057US10600678B2Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnectsINTEL CORP·Filed 2019·Granted Mar 24, 2020·0 cites·16 claims
- 3157US2024241446A1Methods and apparatus to reduce extreme ultraviolet light for photolithographyINTEL CORP·Filed 2024·Application pending·0 cites
- 3255US12080781B2Fabrication of thin film fin transistor structureINTEL CORP·Filed 2020·Granted Sep 3, 2024·0 cites·15 claims
- 3354US2024071955A1Full wafer device with multiple directional indicatorsINTEL CORP·Filed 2022·Application pending·0 cites
- 3454US2024105596A1Integrated circuit devices with angled interconnectsINTEL CORP·Filed 2022·Application pending·0 cites
- 3553US12150297B2Thin film transistors having a backside channel contact for high density memoryINTEL CORP·Filed 2020·Granted Nov 19, 2024·0 cites·20 claims
- 3653US2023422463A1Static random-access memory devices with angled transistorsINTEL CORP·Filed 2023·Application pending·0 cites
- 3752US2024105798A1Trim patterning for forming angled transistorsSHARMA ABHISHEK A·Filed 2022·Application pending·0 cites
- 3851US2025159953A1Integrated circuit devices with angled transistorsINTEL CORP·Filed 2022·Application pending·0 cites
- 3950US12382721B2Integrated circuit structures having cut metal gates with dielectric spacer fillINTEL CORP·Filed 2021·Granted Aug 5, 2025·0 cites·18 claims
- 4050US11950407B2Memory architecture with shared bitline at back-end-of-lineINTEL CORP·Filed 2020·Granted Apr 2, 2024·0 cites·23 claims
- 4148US11056397B2Directional spacer removal for integrated circuit structuresINTEL CORP·Filed 2017·Granted Jul 6, 2021·0 cites·19 claims
- 4247US12446208B2Multilevel wordline assembly for embedded DRAMINTEL CORP·Filed 2021·Granted Oct 14, 2025·0 cites·11 claims
- 4346US2022189957A1Transistors, memory cells, and arrangements thereofINTEL CORP·Filed 2020·Application pending·0 cites
- 4445US2023290825A1Integrated circuit structures with backside self-aligned conductive source or drain contactINTEL CORP·Filed 2022·Application pending·0 cites
- 4542US10811351B2Preformed interlayer connections for integrated circuit devicesINTEL CORP·Filed 2016·Granted Oct 20, 2020·0 cites·20 claims
- 4641US2009124084A1Fabrication of sub-resolution features for an integrated circuitTAN ELLIOT·Filed 2007·Application pending·0 cites
- 4739US2009263751A1Methods for double patterning photoresistSIVAKUMAR SWAMINATHAN·Filed 2008·Application pending·0 cites
- 4837US2006000796A1Method for controlling critical dimensions and etch biasTAN ELLIOT·Filed 2004·Application pending·0 cites
- 4937US2020066521A1Colored self-aligned subtractive patterningINTEL CORP·Filed 2017·Application pending·0 cites
- 5032US2018123038A1Apparatus and method for fabricating a high density memory arrayINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →