Inventor · disambiguated record
Feroze P. Taraporevala
Also filed as: TARAPOREVALA FEROZE · TARAPOREVALA FEROZE P · TARAPOREVALA FEROZE PESHOTAN
11 granted patents·533 citations·filing 1998–2012
92Inventor score
Files withSYNOPSYS INC4LIU JINFENG2MONTEREY DESIGN SYSTEMS INC2GHANTA PRAVEEN1MONTEREY DESIGN SYSTEMS1
Top patents by PatentIndex Score
11 records- 0196US8204730B2Generating variation-aware library data with efficient device mismatch characterizationLIU JINFENG·Filed 2008·Granted Jun 19, 2012·81 cites·36 claims
- 0291US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 0389US8713501B1Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniquesSYNOPSYS INC·Filed 2012·Granted Apr 29, 2014·14 cites·23 claims
- 0488US8615727B2Simultaneous multi-corner static timing analysis using samples-based static timing infrastructureGHANTA PRAVEEN·Filed 2010·Granted Dec 24, 2013·29 cites·32 claims
- 0588US6961916B2Placement method for integrated circuit design using topo-clusteringSYNOPSYS INC·Filed 2002·Granted Nov 1, 2005·45 cites·7 claims
- 0687US6442743B1Placement method for integrated circuit design using topo-clusteringMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Aug 27, 2002·126 cites·13 claims
- 0784US7506293B2Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysisSYNOPSYS INC·Filed 2006·Granted Mar 17, 2009·14 cites·15 claims
- 0874US8321824B2Multiple-power-domain static timing analysisZEJDA JINDRICH·Filed 2009·Granted Nov 27, 2012·8 cites·24 claims
- 0970US7774731B2Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysisSYNOPSYS INC·Filed 2008·Granted Aug 10, 2010·4 cites·2 claims
- 1049US8666722B2Efficient data compression for vector-based static timing analysisLIU JINFENG·Filed 2010·Granted Mar 4, 2014·1 cites·68 claims
- 1137US6385760B2System and method for concurrent placement of gates and associated wiringMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted May 7, 2002·9 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →