Inventor · disambiguated record
Florentin Dartu
Also filed as: DARTU FLORENTIN
7 granted patents·4 pending applications·23 citations·filing 2001–2024
80Inventor score
Top patents by PatentIndex Score
11 records- 0184US8701075B2Recursive hierarchical static timing analysisSYNOPSYS INC·Filed 2013·Granted Apr 15, 2014·9 cites·20 claims
- 0278US10678989B2Method and system for sigma-based timing optimizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 9, 2020·2 cites·20 claims
- 0377US2024370629A1Method of generating netlist including proximity-effect-inducer (pei) parametersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0472US2023385512A1Method of generating netlist including proximity-effect-inducer (pei) parametersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 0567US12086522B2Method of generating netlist including proximity-effect-inducer (PEI) parametersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 10, 2024·0 cites·20 claims
- 0665US8443328B2Recursive hierarchical static timing analysisDARTU FLORENTIN·Filed 2010·Granted May 14, 2013·3 cites·19 claims
- 0763US8042010B2Two-phase clock-stalling technique for error detection and error correctionSYNOPSYS INC·Filed 2008·Granted Oct 18, 2011·3 cites·20 claims
- 0862US11176305B2Method and system for sigma-based timing optimizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 16, 2021·0 cites·20 claims
- 0954US2025156618A1Systems and methods for solving ir violationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 1050US2024143880A1Integrated circuit design method and systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 1144US6498498B1Apparatus and method for applying reciprocity to frequency-domain noise analysisINTEL CORP·Filed 2001·Granted Dec 24, 2002·6 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →