Method of generating netlist including proximity-effect-inducer (pei) parameters

Abstract

A method (of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells) includes generating a netlist which represents the subset, the generating a netlist including: In some embodiments, for each TWEI cell represented in the netlist, and for a given transistor in a given well in a given cell, expanding the netlist to include one or more proximity-effect-inducer (PEI) parameters, each PEI parameter being related to an intra-cell physical proximity of the given transistor to an edge of the given well (given well-edge).

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells, the method comprising:
 generating a netlist which represents the subset, the generating a netlist including:
 for each TWEI cell represented in the netlist, and
 for a given transistor in a given well in a given cell,
 expanding the netlist to include one or more proximity-effect-inducer (PEI) parameters, each PEI parameter being related to an intra-cell physical proximity of the given transistor to an edge of the given well (given well-edge). 
 
 
   
     
     
         2 . The method of  claim 1 , wherein:
 for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell,
 the one or more PEI parameters include:
 a local PEI parameter; and 
 a global PEI parameter; 
 
   the local PEI parameter is represents a distance between the given transistor and the given well-edge;   the local PEI parameter is based on the global PEI parameter; and   the global PEI is a variable common to the given cell and one or more additional cells represented in the netlist.   
     
     
         3 . The method of  claim 2 , wherein:
 the given transistor includes one or more fins; and   the distance between the given transistor and the given well-edge is a distance between a nearest fin and the given well-edge, the nearest fin being one amongst the one or more fins that is nearest to the given well-edge.   
     
     
         4 . The method of  claim 2 , wherein:
 the local PEI parameter is based at least in part on an integral of an expected value of a first order distribution for scattered well dopants.   
     
     
         5 . The method of  claim 4 , wherein:
 the local PEI parameter is also based at least in part on an integral of an expected value of a second order distribution for scattered well dopants.   
     
     
         6 . The method of  claim 2 , wherein:
 for each TWEI cell configured according to complementary metal-oxide-semiconductor (CMOS) technology (CMOS cell) that is represented in the netlist, and for an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor in a given CMOS cell, the one or more PEI parameters include:
 a first local PEI parameter; 
 a second local PEI parameter; 
 a first global PEI parameter; and 
 a second global PEI parameter; 
   the first local PEI parameter is based on a distance between the PMOS transistor and a corresponding well-edge of an N-type well;   the second local PEI parameter is based on a distance between the NMOS transistor and a corresponding well-edge of a P-type well;   the first global PEI parameter is a variable common to the given CMOS cell and one or more additional CMOS cells represented in the netlist; and   the second global PEI parameter is a variable common to the given CMOS cell and the one or more additional CMOS cells represented in the netlist.   
     
     
         7 . The method of  claim 6 , wherein:
 each of the first and second local PEI parameters is based on an integral of an expected value of a first order distribution for scattered well dopants.   
     
     
         8 . The method of  claim 6 , wherein:
 for each TWEI cell configured according to complementary metal-oxide-semiconductor (CMOS) technology (CMOS cell) that is represented in the netlist, and for the N-type metal-oxide-semiconductor (NMOS) transistor and the P-type metal-oxide-semiconductor (PMOS) transistor in the given CMOS cell, the one or more PEI parameters further include:
 a third local PEI parameter; 
 a fourth local PEI parameter; 
 a third global PEI parameter; and 
 a fourth global PEI parameter; 
   the third local PEI parameter is based on a distance between the PMOS transistor and a corresponding well-edge of an N-type well;   the fourth local PEI parameter is based on a distance between the NMOS transistor and a corresponding well-edge of a P-type well;   the third global PEI parameter is a variable common to the given CMOS cell and the one or more additional CMOS cells represented in the netlist; and   the fourth global PEI parameter is a variable common to the given CMOS cell and the one or more additional CMOS cells represented in the netlist.   
     
     
         9 . The method of  claim 8 , wherein:
 each of the third and fourth local PEI parameters is based on an integral of an expected value of a second order distribution for scattered well dopants.   
     
     
         10 . The method of  claim 1 , further comprising:
 performing a simulation of the semiconductor device, the simulation being based on the netlist; and   revising the layout diagram based on results of the simulation resulting in a revised layout diagram.   
     
     
         11 . The method of  claim 10 , further comprising:
 based on the revised layout diagram, at least one of:
 (A) making one or more photolithographic exposure; 
 (B) fabricating one or more semiconductor masks; or 
 (C) fabricating at least one component in a layer of a semiconductor integrated circuit. 
   
     
     
         12 . The method of  claim 1 , wherein:
 for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell,
 the one or more PEI parameters include:
 a global PEI parameter, the global PEI being a variable common to the given cell and one or more additional cells represented in the netlist. 
 
   
     
     
         13 . The method of  claim 12 , wherein:
 for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell,
 the one or more PEI parameters include:
 a local PEI parameter; 
 
   the local PEI parameter represents a proximity relationship between the given transistor and the given well-edge; and   the local PEI parameter is a function of the global PEI parameter.   
     
     
         14 . The method of  claim 1 , wherein:
 relative to a first direction, a first neighbor-specific PEI (NSPE) parameter represents a first distance from a first side of a subject cell to a first structure in a first neighbor cell that has a proximity effect upon the subject cell; and   relative to the first direction, a second NSPE parameter represents a second distance from a second side of the subject cell to a second structure in a second neighbor cell that has a proximity effect upon the subject cell;   
     
     
         15 . A system for fabricating a semiconductor device, the system comprising:
 at least one processor;   at least one non-transitory computer readable medium that stores for which stored therein includes computer executable code and a layout diagram corresponding to the semiconductor device; and   the at least one non-transitory computer readable medium, the computer-executable code and the at least one processor being configured to cause the system to do as follows including:
 generating a netlist which represents subject cells in the layout diagram, the generating a netlist including:
 for each subject cell represented in the netlist,
 expanding the netlist to include one or more inter-cell proximity-effect-inducer (PEI) parameters, each inter-cell PEI parameter being related to a given type of structure in a given neighbor cell that induces an inter-cell proximity effect upon a given subject cell. 
 
 
   
     
     
         16 . The system of  claim 15 , wherein:
 for a subset of the subject cells in the netlist, the given type of structure in the given neighbor cell is a rectangular structure; and   the at least one non-transitory computer readable medium, the computer-executable code and the at least one processor being configured to cause the system to do as follows including:
 for the subset of the subject cells in the netlist, the generating a netlist includes:
 configuring a corresponding one of the one or more inter-cell PEI parameters to be footprint parameter that represents a footprint of the rectangular structure in the given neighbor cell. 
 
   
     
     
         17 . The system of  claim 15 , wherein:
 for a subset of the subject cells in the netlist, the given type of structure in the given neighbor cell is an active region (AR); and   the at least one non-transitory computer readable medium, the computer-executable code and the at least one processor being configured to cause the system to do as follows including:
 for the subset of the subject cells in the netlist, the generating a netlist includes:
 configuring a corresponding one of the one or more inter-cell PEI parameters to be AR-density parameter that represents a density of active regions in the given neighbor cell. 
 
   
     
     
         18 . A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells, the method comprising generating a netlist which represents the subset, the generating a netlist including:
 for each TWEI cell represented in the netlist, and for a given transistor in a given well in a given cell,
 expanding the netlist to include proximity-effect-inducer (PEI) parameters, the PEI parameters including: 
 relative to a first direction, a first neighbor-specific PEI (NSPE) parameter representing a first distance from a first side of a subject cell to a first structure in a first neighbor cell that has a proximity effect upon the subject cell; and 
 relative to the first direction, a second NSPE parameter representing a second distance from a second side of the subject cell to a second structure in a second neighbor cell that has a proximity effect upon the subject cell. 
   
     
     
         19 . The method of  claim 18 , wherein:
 for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell,
 the PEI parameters further include:
 a global PEI parameter, the global PEI being a variable common to the given cell and one or more additional cells represented in the netlist. 
 
   
     
     
         20 . The method of  claim 19 , wherein:
 for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell,
 the PEI parameters further include:
 a local PEI parameter; 
 
   the local PEI parameter represents an intra-cell physical proximity relationship between the given transistor and an edge of the given well; and   the local PEI parameter is a function of the global PEI parameter.