Inventor · disambiguated record
Gil Balog
Also filed as: BALOG GIL
15 granted patents·3 pending applications·88 citations·filing 2006–2014
93Inventor score
Top patents by PatentIndex Score
18 records- 0191US7340359B2Augmenting semiconductor's devices quality and reliabilityOPTIMALTEST LTD·Filed 2006·Granted Mar 4, 2008·23 cites·61 claims
- 0289US7969174B2Systems and methods for test time outlier detection and correction in integrated circuit testingOPTIMALTEST LTD·Filed 2009·Granted Jun 28, 2011·13 cites·15 claims
- 0386US9529036B2Systems and methods for test time outlier detection and correction in integrated circuit testingOPTIMAL PLUS LTD·Filed 2014·Granted Dec 27, 2016·4 cites·18 claims
- 0484US7532024B2Methods and systems for semiconductor testing using reference diceOPTIMALTEST LTD·Filed 2006·Granted May 12, 2009·9 cites·17 claims
- 0579US8421494B2Systems and methods for test time outlier detection and correction in integrated circuit testingBALOG GIL·Filed 2011·Granted Apr 16, 2013·3 cites·18 claims
- 0678US7528622B2Methods for slow test time detection of an integrated circuit during parallel testingOPTIMAL TEST LTD·Filed 2006·Granted May 5, 2009·8 cites·14 claims
- 0775US8069130B2Methods and systems for semiconductor testing using a testing scenario languageBALOG GIL·Filed 2009·Granted Nov 29, 2011·6 cites·19 claims
- 0872US7777515B2Methods and systems for semiconductor testing using reference diceOPTIMALTEST LTD·Filed 2008·Granted Aug 17, 2010·4 cites·22 claims
- 0969US8112249B2System and methods for parametric test time reductionGUROV LEONID·Filed 2008·Granted Feb 7, 2012·4 cites·22 claims
- 1067US7737716B2Methods and systems for semiconductor testing using reference diceOPTIMALTEST LTD·Filed 2008·Granted Jun 15, 2010·3 cites·17 claims
- 1167US7679392B2Methods and systems for semiconductor testing using reference diceOPTIMALTEST LTD·Filed 2008·Granted Mar 16, 2010·3 cites·2 claims
- 1264US7567947B2Methods and systems for semiconductor testing using a testing scenario languageOPTIMALTEST LTD·Filed 2006·Granted Jul 28, 2009·4 cites·29 claims
- 1362US10118200B2System and method for binning at final testLINDE REED·Filed 2009·Granted Nov 6, 2018·3 cites·28 claims
- 1459US8781773B2System and methods for parametric testingGUROV LEONID·Filed 2011·Granted Jul 15, 2014·1 cites·59 claims
- 1554US8872538B2Systems and methods for test time outlier detection and correction in integrated circuit testingOPTIMALTEST LTD·Filed 2013·Granted Oct 28, 2014·0 cites·18 claims
- 1643US2012109874A1Methods and systems for semiconductor testing using a testing scenario languageBALOG GIL·Filed 2011·Application pending·0 cites
- 1739US2008114558A1Augmenting semiconductor's devices quality and reliabilityOPTIMAL TEST LTD·Filed 2008·Application pending·0 cites
- 1837US2009013218A1Datalog management in semiconductor testingOPTIMAL TEST LTD·Filed 2007·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Gil Balog files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →