Inventor · disambiguated record
Guoxiang Ning
Also filed as: NING GUOXIANG
42 granted patents·2 pending applications·56 citations·filing 2009–2021
96Inventor score
Files withGLOBALFOUNDRIES INC38GLOBALFOUNDRIES US INC3GLOBALFOUNDRIES SG PTE LTD2CHARTERED SEMICONDUCTOR MFG1
Top patents by PatentIndex Score
44 records- 0194US10199271B1Self-aligned metal wire on contact structure and method for forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 5, 2019·10 cites·8 claims
- 0294US9500945B1Pattern classification based proximity corrections for reticle fabricationGLOBALFOUNDRIES SG PTE LTD·Filed 2015·Granted Nov 22, 2016·9 cites·20 claims
- 0390US10423078B1FinFET cut isolation opening revision to compensate for overlay inaccuracyGLOBALFOUNDRIES INC·Filed 2019·Granted Sep 24, 2019·6 cites·11 claims
- 0486US10386726B2Geometry vectorization for mask process correctionGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 20, 2019·3 cites·17 claims
- 0584US10957701B1Fin-based anti-fuse device for integrated circuit (IC) products, methods of making such an anti-fuse device and IC products comprising such an anti-fuse deviceGLOBALFOUNDRIES US INC·Filed 2019·Granted Mar 23, 2021·4 cites·12 claims
- 0683US10892222B1Anti-fuse for an integrated circuit (IC) product and method of making such an anti-fuse for an IC productGLOBALFOUNDRIES INC·Filed 2019·Granted Jan 12, 2021·4 cites·20 claims
- 0777US11037937B2SRAM bit cells formed with dummy structuresGLOBALFOUNDRIES US INC·Filed 2019·Granted Jun 15, 2021·2 cites·17 claims
- 0877US10896874B2Interconnects separated by a dielectric region formed using removable sacrificial plugsGLOBALFOUNDRIES INC·Filed 2019·Granted Jan 19, 2021·2 cites·13 claims
- 0976US10324381B1FinFET cut isolation opening revision to compensate for overlay inaccuracyGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 18, 2019·2 cites·4 claims
- 1076US9329471B1Achieving a critical dimension target based on resist characteristicsGLOBALFOUNDRIES INC·Filed 2014·Granted May 3, 2016·2 cites·16 claims
- 1176US8907496B1Circuit structures and methods of fabrication with enhanced contact via electrical connectionGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 9, 2014·4 cites·20 claims
- 1275US10923388B2Gap fill void and connection structuresGLOBALFOUNDRIES INC·Filed 2019·Granted Feb 16, 2021·1 cites·18 claims
- 1368US10714422B2Anti-fuse with self aligned via patterningGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 14, 2020·1 cites·18 claims
- 1468US10002827B2Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 19, 2018·1 cites·9 claims
- 1568US9368453B2Overlay mark dependent dummy fill to mitigate gate height variationGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 14, 2016·1 cites·15 claims
- 1667US9606432B2Alternating space decomposition in circuit structure fabricationGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 28, 2017·1 cites·16 claims
- 1767US9250538B2Efficient optical proximity correction repair flow method and apparatusGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 2, 2016·1 cites·13 claims
- 1866US11651992B2Gap fill void and connection structuresGLOBALFOUNDRIES US INC·Filed 2021·Granted May 16, 2023·0 cites·20 claims
- 1961US9535319B2Reticle, system comprising a plurality of reticles and method for the formation thereofGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 3, 2017·1 cites·28 claims
- 2059US9236301B2Customized alleviation of stresses generated by through-substrate via(S)GLOBALFOUNDRIES INC·Filed 2013·Granted Jan 12, 2016·1 cites·17 claims
- 2157US9658531B2Semiconductor device resolution enhancement by etching multiple sides of a maskGLOBALFOUNDRIES INC·Filed 2014·Granted May 23, 2017·0 cites·11 claims
- 2256US9323882B2Metrology pattern layout and method of use thereofGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 26, 2016·0 cites·18 claims
- 2354US10816483B2Double pass diluted ultraviolet reticle inspectionGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·0 cites·12 claims
- 2454US9252061B2Overlay mark dependent dummy fill to mitigate gate height variationGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 2, 2016·0 cites·13 claims
- 2554US8895211B2Semiconductor device resolution enhancement by etching multiple sides of a maskGLOBALFOUNDRIES INC·Filed 2012·Granted Nov 25, 2014·0 cites·17 claims
- 2653US9817940B2Method wherein test cells and dummy cells are included into a layout of an integrated circuitGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 14, 2017·0 cites·16 claims
- 2752US10804170B2Device/health of line (HOL) aware eBeam based overlay (EBO OVL) structureGLOBALFOUNDRIES INC·Filed 2019·Granted Oct 13, 2020·0 cites·14 claims
- 2852US10770344B2Chamferless interconnect vias of semiconductor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Sep 8, 2020·0 cites·20 claims
- 2952US10627720B2Overlay mark structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 21, 2020·0 cites·13 claims
- 3052US7923180B2Cross technology reticlesCHARTERED SEMICONDUCTOR MFG·Filed 2009·Granted Apr 12, 2011·0 cites·18 claims
- 3151US9864831B2Metrology pattern layout and method of use thereofGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 9, 2018·0 cites·20 claims
- 3250US10727120B2Controlling back-end-of-line dimensions of semiconductor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 28, 2020·0 cites·14 claims
- 3350US9791772B2Monitoring pattern for devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Oct 17, 2017·0 cites·13 claims
- 3449US9384318B2Mask error compensation by optical modeling calibrationGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 5, 2016·0 cites·17 claims
- 3547US10777413B2Interconnects with non-mandrel cuts formed by early block patterningGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 15, 2020·0 cites·19 claims
- 3647US9672313B2Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 6, 2017·0 cites·11 claims
- 3747US9672312B2Method wherein test cells and dummy cells are included into a layout of an integrated circuitGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 6, 2017·0 cites·22 claims
- 3847US9645486B2Multiple threshold convergent OPC modelGLOBALFOUNDRIES INC·Filed 2014·Granted May 9, 2017·0 cites·17 claims
- 3946US10332745B2Dummy assist features for pattern supportGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 25, 2019·0 cites·17 claims
- 4045US10483214B2Overlay structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Nov 19, 2019·0 cites·14 claims
- 4144US10642160B2Self-aligned quadruple patterning pitch walking solutionGLOBALFOUNDRIES INC·Filed 2018·Granted May 5, 2020·0 cites·20 claims
- 4244US9136223B2Forming alignment mark and resulting markGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 15, 2015·0 cites·17 claims
- 4343US2015028482A1Device layout for reducing through-silicon-via stressGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 4439US2019278166A1Photolithography system and method using a reticle with multiple different sets of redundant framed mask patternsGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →