Inventor · disambiguated record
Habeeb Farah
Also filed as: FARAH HABEEB · FARAH HABEEB A
16 granted patents·1 pending application·52 citations·filing 2005–2022
91Inventor score
Top patents by PatentIndex Score
17 records- 0192US11514219B1System and method for assertion-based formal verification using cached metadataCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Nov 29, 2022·7 cites·20 claims
- 0290US10789404B1System, method, and computer program product for generating a formal verification modelCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Sep 29, 2020·7 cites·20 claims
- 0382US10983758B1System, method, and computer program product for automatically inferring case-split hints in equivalence checking of an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Apr 20, 2021·3 cites·20 claims
- 0481US9158874B1Formal verification coverage metrics of covered events for circuit design propertiesJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Oct 13, 2015·6 cites·20 claims
- 0579US8826201B1Formal verification coverage metrics for circuit design propertiesJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Sep 2, 2014·5 cites·18 claims
- 0678US10984161B1System, method, and computer program product for sequential equivalence checking in formal verificationCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Apr 20, 2021·2 cites·17 claims
- 0774US7346864B2Logic design development tool and methodINTEL CORP·Filed 2005·Granted Mar 18, 2008·11 cites·19 claims
- 0871US11023357B1Method and system for sequential equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jun 1, 2021·3 cites·19 claims
- 0970US10853546B1Method and system for sequential equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Dec 1, 2020·2 cites·19 claims
- 1070US10782767B1System, method, and computer program product for clock gating in a formal verificationCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 22, 2020·2 cites·17 claims
- 1169US9177089B2Formal verification coverage metrics for circuit design propertiesHANNA ZIYAD E·Filed 2014·Granted Nov 3, 2015·3 cites·20 claims
- 1265US10546083B1System, method, and computer program product for improving coverage accuracy in formal verificationCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 28, 2020·1 cites·18 claims
- 1353US12487905B1User interface for formal verification of computer instructions for compatibility with a compiler architectureCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Dec 2, 2025·0 cites·20 claims
- 1447US11080448B1Method and system for formal bug huntingCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Aug 3, 2021·0 cites·14 claims
- 1543US10452798B1System, method, and computer program product for filtering one or more failures in a formal verificationCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 22, 2019·0 cites·20 claims
- 1642US2006224657A1Method, system and apparatus for quotient digit generationINTEL CORP·Filed 2005·Application pending·0 cites
- 1741US11520964B1Method and system for assertion-based formal verification using unique signature valuesCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Dec 6, 2022·0 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →