Inventor · disambiguated record
Hoong Shing Wong
Also filed as: WONG HOONG SHING
12 granted patents·4 pending applications·511 citations·filing 2012–2025
91Inventor score
Top patents by PatentIndex Score
16 records- 0196US9252238B1Semiconductor structures with coplanar recessed gate layers and fabrication methodsGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 2, 2016·427 cites·20 claims
- 0294US9006066B2FinFET with active region shaped structures and channel separationGLOBALFOUNDRIES INC·Filed 2013·Granted Apr 14, 2015·19 cites·10 claims
- 0393US8946029B2Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regionsGLOBALFOUNDRIES INC·Filed 2012·Granted Feb 3, 2015·16 cites·7 claims
- 0492US8906768B2Wrap around stressor formationGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 9, 2014·15 cites·20 claims
- 0590US9153496B2Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regionsGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 6, 2015·10 cites·20 claims
- 0687US2025308904A1Methods for doping high-k metal gates for tuning threshold voltagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0785US10128333B2FinFET with isolated source and drainGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 13, 2018·4 cites·14 claims
- 0885US9147680B2Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 29, 2015·10 cites·19 claims
- 0984US2024379365A1Methods for doping high-k metal gates for tuning threshold voltagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1081US9337340B2FinFET with active region shaped structures and channel separationGLOBALFOUNDRIES INC·Filed 2015·Granted May 10, 2016·3 cites·6 claims
- 1179US12463040B2Methods for doping high-K metal gates for tuning threshold voltagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Nov 4, 2025·0 cites·20 claims
- 1277US8940650B2Methods for fabricating integrated circuits utilizing silicon nitride layersGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 27, 2015·4 cites·19 claims
- 1371US9159567B1Replacement low-K spacerGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 13, 2015·3 cites·12 claims
- 1466US11342188B2Methods for doping high-k metal gates for tuning threshold voltagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted May 24, 2022·0 cites·20 claims
- 1549US2015221726A1Finfet with isolated source and drainGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 1641US2014131777A1Integrated circuits and methods for fabricating integrated circuits with salicide contacts on non-planar source/drain regionsGLOBALFOUNDRIES INC·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →