Finfet with isolated source and drain

Abstract

A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

1 . A method, comprising:
 providing a semiconductor structure, the structure comprising: a semiconductor substrate; at least one raised semiconductor structure coupled to the substrate, and an active region having a source region, a drain region and a channel region therebetween, the active region comprising a layer of epitaxy over a top surface of the at least one raised structure, a dummy gate encompassing the channel region and a spacer on either side of the dummy gate; and   electrically isolating the source region and the drain region from the at least one raised semiconductor structure while the channel region remains coupled thereto.   
     
     
         2 . The method of claim of  claim 1 , wherein the electrically isolating comprises:
 separating the source region and the drain region from the at least one raised semiconductor structure while the channel region remains coupled to the at least one raised semiconductor structure, wherein the separating creates a source region gap and a drain region gap with the at least one raised semiconductor structure; and   filling the source region gap and the drain region gap with at least one electrically insulating material.   
     
     
         3 . The method of  claim 2 , wherein the separating comprises:
 recessing the substrate to expose a portion of the at least one raised semiconductor structure; and   etching the exposed portion of the at least one raised semiconductor structure.   
     
     
         4 . The method of  claim 3 , wherein the exposed portion of the at least one raised semiconductor structure has a length of about 5 nm to about 10 nm. 
     
     
         5 . The method of  claim 2 , further comprising, prior to the filling, reducing defects in the epitaxy and/or substrate caused by the separating. 
     
     
         6 . The method of  claim 5 , wherein reducing defects comprises oxidizing affected surfaces of the epitaxy and the at least one raised semiconductor structure. 
     
     
         7 . The method of  claim 2 , wherein the filling comprises conformally depositing the at least one insulating material over the source region and the drain region, and in the source and drain region gaps. 
     
     
         8 . The method of  claim 2 , wherein the semiconductor structure further comprises at least one other type of semiconductor device, the method further comprising masking the at least one other type of semiconductor device prior to the separating and the filling. 
     
     
         9 . A semiconductor structure, comprising:
 a semiconductor substrate;   at least one raised semiconductor structure coupled to the substrate; and   an active region for each of the at least one raised semiconductor structure having a source region, a drain region and a channel region therebetween, wherein the active region comprises a layer of epitaxy coupled to the at least one raised semiconductor structure at the channel region, the source region and the drain region being isolated from the at least one raised semiconductor structure by a layer of at least one electrically insulating material.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein the layer of at least one insulating material has a thickness of about 5 nm to about 10 nm. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein the layer of at least one insulating material comprises at least one oxide. 
     
     
         12 . The semiconductor structure of  claim 9 , wherein the layer of at least one insulating material comprises at least one nitride. 
     
     
         13 . The semiconductor structure of  claim 9 , wherein the semiconductor substrate comprises a bulk semiconductor substrate, wherein the at least one raised semiconductor structure comprises a plurality of raised semiconductor structures. 
     
     
         14 . The semiconductor structure of  claim 13 , wherein the bulk semiconductor substrate comprises at least two different types of semiconductor devices. 
     
     
         15 . The semiconductor structure of  claim 9 , further comprising:
 a dummy gate encompassing the channel region; and   a spacer on either side of the dummy gate with a cap thereover.   
     
     
         16 . The semiconductor structure of  claim 9 , wherein the epitaxy comprises epitaxial silicon. 
     
     
         17 . The semiconductor structure of  claim 9 , wherein the epitaxy comprises epitaxial silicon germanium. 
     
     
         18 . The semiconductor structure of  claim 9 , wherein the epitaxy comprises at least one material from each of periodic table column III and column V. 
     
     
         19 . The semiconductor structure of  claim 9 , wherein the epitaxy comprises at least one material from each of periodic table column II and column VI.