Inventor · disambiguated record
Hsiang-Huan Lee
Also filed as: LEE HSIANG-HUAN
65 granted patents·1 pending application·272 citations·filing 2008–2019
98Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD35TAIWAN SEMICONDUCTOR MFG24LEE HSIANG-HUAN1LEE MING-HAN1LU CHIH-WEI1
Top patents by PatentIndex Score
66 records- 0197US9773676B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Sep 26, 2017·17 cites·19 claims
- 0297US9177797B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 3, 2015·28 cites·20 claims
- 0396US9892933B2Lithography using multilayer spacer for reduced spacer footingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Feb 13, 2018·15 cites·20 claims
- 0494US10014175B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 3, 2018·7 cites·20 claims
- 0594US8735280B1Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted May 27, 2014·13 cites·19 claims
- 0693US9728503B2Via pre-fill on back-end-of-the-line interconnect layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 8, 2017·9 cites·20 claims
- 0793US9633949B2Copper etching integration schemeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 25, 2017·7 cites·20 claims
- 0891US9343356B2Back end of the line (BEOL) interconnect schemeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted May 17, 2016·14 cites·19 claims
- 0990US9159579B2Lithography using multilayer spacer for reduced spacer footingTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Oct 13, 2015·8 cites·19 claims
- 1090US9030013B2Interconnect structures comprising flexible buffer layersTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted May 12, 2015·9 cites·20 claims
- 1189US9490205B2Integrated circuit interconnects and methods of making sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Nov 8, 2016·6 cites·20 claims
- 1288US9613854B2Method and apparatus for back end of line semiconductor device processingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Apr 4, 2017·6 cites·20 claims
- 1388US9343400B2Dual damascene gap filling processTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted May 17, 2016·9 cites·20 claims
- 1488US9252049B2Method for forming interconnect structure that avoids via recessTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Feb 2, 2016·7 cites·14 claims
- 1588US9142505B2Method and apparatus for back end of line semiconductor device processingTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 22, 2015·9 cites·20 claims
- 1687US9318439B2Interconnect structure and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Apr 19, 2016·6 cites·20 claims
- 1786US9466525B2Interconnect structures comprising flexible buffer layersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Oct 11, 2016·4 cites·20 claims
- 1885US8013445B2Low resistance high reliability contact via and metal line structure for semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Sep 6, 2011·12 cites·20 claims
- 1984US9818644B2Interconnect structure and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Nov 14, 2017·3 cites·20 claims
- 2084US8728936B1Copper etching integration schemeTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted May 20, 2014·7 cites·18 claims
- 2183US9646932B2Method for forming interconnect structure that avoids via recessTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 9, 2017·3 cites·20 claims
- 2283US9640431B2Method for via plating with seed layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 2, 2017·2 cites·20 claims
- 2383US9373586B2Copper etching integration schemeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jun 21, 2016·4 cites·17 claims
- 2483US9269668B2Interconnect having air gaps and polymer wrapped conductive linesTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Feb 23, 2016·4 cites·20 claims
- 2582US9054163B2Method for via plating with seed layerTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jun 9, 2015·3 cites·20 claims
- 2681US10020259B2Copper etching integration schemeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 10, 2018·2 cites·20 claims
- 2781US9054161B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Jun 9, 2015·3 cites·20 claims
- 2880US9837310B2Method of manufacturing a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 5, 2017·4 cites·20 claims
- 2980US9318364B2Semiconductor device metallization systems and methodsTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Apr 19, 2016·3 cites·20 claims
- 3080US8749060B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Jun 10, 2014·4 cites·20 claims
- 3179US8912041B2Method for forming recess-free interconnect structureTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 16, 2014·4 cites·20 claims
- 3277US8735278B2Copper etch scheme for copper interconnect structureLEE MING HAN·Filed 2012·Granted May 27, 2014·6 cites·11 claims
- 3377US8106512B2Low resistance high reliability contact via and metal line structure for semiconductor deviceLEE HSIANG-HUAN·Filed 2010·Granted Jan 31, 2012·5 cites·20 claims
- 3476US9093501B2Interconnection wires of semiconductor devicesTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Jul 28, 2015·3 cites·20 claims
- 3576US8835304B2Method of semiconductor integrated circuit fabricationLU CHIH WEI·Filed 2012·Granted Sep 16, 2014·4 cites·20 claims
- 3675US8778794B1Interconnection wires of semiconductor devicesTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Jul 15, 2014·3 cites·20 claims
- 3773US9281263B2Interconnect structure including a continuous conductive bodyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Mar 8, 2016·3 cites·18 claims
- 3871US10121698B2Method of manufacturing a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Nov 6, 2018·1 cites·20 claims
- 3971US9330989B2System and method for chemical-mechanical planarization of a metal layerTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted May 3, 2016·2 cites·20 claims
- 4071US9324608B2Method for via plating with seed layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Apr 26, 2016·1 cites·20 claims
- 4171US9219033B2Via pre-fill on back-end-of-the-line interconnect layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 22, 2015·2 cites·20 claims
- 4269US9496170B2Interconnect having air gaps and polymer wrapped conductive linesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Nov 15, 2016·1 cites·20 claims
- 4368US9484302B2Semiconductor devices and methods of manufacture thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Nov 1, 2016·1 cites·20 claims
- 4468US9425089B2Conductive element structure and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Aug 23, 2016·1 cites·20 claims
- 4567US8624396B2Apparatus and method for low contact resistance carbon nanotube interconnectWU HSIEN-CHANG·Filed 2012·Granted Jan 7, 2014·2 cites·20 claims
- 4666US9034756B2Integrated circuit interconnects and methods of making sameTSAI CHENG-HSIUNG·Filed 2012·Granted May 19, 2015·2 cites·20 claims
- 4765US10930552B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 4864US9142509B2Copper interconnect structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Sep 22, 2015·1 cites·20 claims
- 4963US11908789B2Selective formation of conductor nanowiresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 20, 2024·0 cites·20 claims
- 5063US9275960B2Integrated circuit formed using spacer-like copper depositionTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Mar 1, 2016·1 cites·20 claims
Showing the top 50 of 66 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →