Inventor · disambiguated record
Hung-Tsun Lin
Also filed as: LIN HUNG-TSUN
9 granted patents·6 pending applications·76 citations·filing 2006–2010
86Inventor score
Technology areasH10W
Top patents by PatentIndex Score
15 records- 0190US7663246B2Stacked chip packaging with heat sink structureCHIPMOS TECHNOLOGIES INC·Filed 2007·Granted Feb 16, 2010·22 cites·20 claims
- 0288US7662672B2Manufacturing process of leadframe-based BGA packagesCHIPMOS TECHNOLOGIES BERMUDA·Filed 2008·Granted Feb 16, 2010·20 cites·19 claims
- 0385US7582953B2Package structure with leadframe on offset chip-stacked structureCHIPMOS TECHNOLOGIES INC·Filed 2007·Granted Sep 1, 2009·16 cites·20 claims
- 0474US7952198B2BGA package with leads on chipCHIPMOS TECHNOLOGIES BERMUDA·Filed 2008·Granted May 31, 2011·7 cites·20 claims
- 0570US7879653B2Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the sameCHIPMOS TECHNOLOGIES BERMUDA·Filed 2008·Granted Feb 1, 2011·4 cites·10 claims
- 0670US7579676B2Leadless leadframe implemented in a leadframe-based BGA packageCHIPMOS TECHNOLOGIES BERMUDA·Filed 2006·Granted Aug 25, 2009·5 cites·7 claims
- 0759US7479706B2Chip package structureCHIPMOS TECHNOLOGIES INC·Filed 2007·Granted Jan 20, 2009·2 cites·10 claims
- 0848US7781898B2IC package reducing wiring layers on substrate and its chip carrierCHIPMOS TECHNOLOGIES INC·Filed 2007·Granted Aug 24, 2010·0 cites·11 claims
- 0946US8026615B2IC package reducing wiring layers on substrate and its carrierCHIPMOS TECHNOLOGIES INC·Filed 2010·Granted Sep 27, 2011·0 cites·13 claims
- 1046US2007222040A1Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the sameCHIPMOS TECHNOLOGIES INC·Filed 2006·Application pending·0 cites
- 1145US2009039533A1Adhesion structure for a package apparatusCHIPMOS TECHNOLOGIES BERMUDA I·Filed 2008·Application pending·0 cites
- 1245US2009189296A1Flip chip quad flat non-leaded package structure and manufacturing method thereof and chip package structureCHIPMOS TECHNOLOGIES INC·Filed 2008·Application pending·0 cites
- 1342US2008029903A1Chip-stacked package structureCHIPMOS TECHNOLOGIES BERMUDA·Filed 2007·Application pending·0 cites
- 1441US2007290301A1Multi-chip stacked package with reduced thicknessCHIPMOS TECHNOLOGIES INC·Filed 2006·Application pending·0 cites
- 1540US2008042277A1BGA package with leads on chip field of the inventionCHIPMOS TECHNOLOGIES INC·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →