Inventor · disambiguated record
Huang Liu
Also filed as: LIU HUANG · LIU HUANG-LIANG
80 granted patents·24 pending applications·432 citations·filing 1999–2018
99Inventor score
Files withGLOBALFOUNDRIES INC59CHARTERED SEMICONDUCTOR MFG14GLOBALFOUNDRIES SG PTE LTD10YU HONG7LIU HUANG4
Top patents by PatentIndex Score
104 records- 0197US9620380B1Methods for fabricating integrated circuits using self-aligned quadruple patterningGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 11, 2017·31 cites·18 claims
- 0297US9466723B1Liner and cap layer for placeholder source/drain contact structure planarization and replacementGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 11, 2016·31 cites·15 claims
- 0397US9455204B110 nm alternative N/P doped fin for SSRW schemeGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 27, 2016·21 cites·20 claims
- 0495US9478625B1Metal resistor using FinFET-based replacement gate processGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 25, 2016·13 cites·20 claims
- 0595US9443956B2Method for forming air gap structure using carbon-containing spacerGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 13, 2016·22 cites·21 claims
- 0694US9087870B2Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 21, 2015·18 cites·19 claims
- 0793US8962474B2Method for forming an air gap around a through-silicon viaYU HONG·Filed 2011·Granted Feb 24, 2015·17 cites·8 claims
- 0893US8722485B1Integrated circuits having replacement gate structures and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2013·Granted May 13, 2014·19 cites·22 claims
- 0992US9123771B2Shallow trench isolation integration methods and devices formed therebyGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 1, 2015·13 cites·19 claims
- 1091US9589807B1Method for eliminating interlayer dielectric dishing and controlling gate height uniformityGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 7, 2017·11 cites·20 claims
- 1188US9425127B2Method for forming an air gap around a through-silicon viaGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Aug 23, 2016·8 cites·17 claims
- 1287US9153693B2FinFET gate with insulated vias and method of making sameGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 6, 2015·9 cites·17 claims
- 1387US7566656B2Method and apparatus for providing void structuresCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Jul 28, 2009·17 cites·31 claims
- 1486US8518775B2Integration of eNVM, RMG, and HKMG modulesLIU HUANG·Filed 2011·Granted Aug 27, 2013·12 cites·18 claims
- 1584US9793169B1Methods for forming mask layers using a flowable carbon-containing silicon dioxide materialGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 17, 2017·3 cites·20 claims
- 1682US9490129B2Integrated circuits having improved gate structures and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 8, 2016·5 cites·20 claims
- 1782US9385192B2Shallow trench isolation integration methods and devices formed therebyGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 5, 2016·3 cites·7 claims
- 1882US8916939B2Reliable contactsGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Dec 23, 2014·5 cites·15 claims
- 1982US8803254B2Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structuresGLOBALFOUNDRIES INC·Filed 2012·Granted Aug 12, 2014·8 cites·11 claims
- 2082US6211040B1Two-step, low argon, HDP CVD oxide deposition processCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Apr 3, 2001·80 cites·20 claims
- 2181US7745320B2Method for reducing silicide defects in integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Jun 29, 2010·7 cites·21 claims
- 2280US9401416B2Method for reducing gate height variation due to overlapping masksGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 26, 2016·4 cites·21 claims
- 2380US7892900B2Integrated circuit system employing sacrificial spacersGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Feb 22, 2011·9 cites·20 claims
- 2477US9666476B2Dimension-controlled via formation processingGLOBALFOUNDRIES INC·Filed 2015·Granted May 30, 2017·2 cites·19 claims
- 2577US9275898B1Method to improve selectivity cobalt cap processGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 1, 2016·3 cites·20 claims
- 2677US8987134B2Reliable interconnect for semiconductor deviceGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Mar 24, 2015·4 cites·11 claims
- 2777US8940650B2Methods for fabricating integrated circuits utilizing silicon nitride layersGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 27, 2015·4 cites·19 claims
- 2877US8405222B2Integrated circuit system with via and method of manufacture thereofYU HONG·Filed 2010·Granted Mar 26, 2013·5 cites·20 claims
- 2976US9329471B1Achieving a critical dimension target based on resist characteristicsGLOBALFOUNDRIES INC·Filed 2014·Granted May 3, 2016·2 cites·16 claims
- 3076US8716150B1Method of forming a low-K dielectric filmGLOBALFOUNDRIES INC·Filed 2013·Granted May 6, 2014·3 cites·20 claims
- 3174US9324841B2Methods for preventing oxidation damage during FinFET fabricationGLOBALFOUNDRIES INC·Filed 2013·Granted Apr 26, 2016·3 cites·20 claims
- 3273US8993446B2Method of forming a dielectric filmGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 31, 2015·2 cites·7 claims
- 3373US8354347B2Method of forming high-k dielectric stop layer for contact hole openingGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Jan 15, 2013·6 cites·29 claims
- 3472US9305832B2Dimension-controlled via formation processingGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 5, 2016·2 cites·18 claims
- 3572US9230822B1Uniform gate height for mixed-type non-planar semiconductor devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 5, 2016·2 cites·9 claims
- 3672US8877637B2Damascene process for aligning and bonding through-silicon-via based 3D integrated circuit stacksYU HONG·Filed 2011·Granted Nov 4, 2014·3 cites·19 claims
- 3771US10559470B2Capping structureGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 11, 2020·1 cites·18 claims
- 3871US9093561B2Modified, etch-resistant gate structure(s) facilitating circuit fabricationGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 28, 2015·2 cites·20 claims
- 3970US7855143B2Interconnect capping layer and method of fabricationCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Dec 21, 2010·3 cites·19 claims
- 4069US8940637B2Method for forming through silicon via with wafer backside protectionLEONG LUP SAN·Filed 2012·Granted Jan 27, 2015·3 cites·11 claims
- 4168US8519482B2Reliable contactsYU HONG·Filed 2011·Granted Aug 27, 2013·2 cites·17 claims
- 4267US9606432B2Alternating space decomposition in circuit structure fabricationGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 28, 2017·1 cites·16 claims
- 4367US9455188B2Through silicon via device having low stress, thin film gaps and methods for forming the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 27, 2016·2 cites·11 claims
- 4466US9754837B1Controlling within-die uniformity using doped polishing materialGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 5, 2017·1 cites·16 claims
- 4566US9318440B2Formation of carbon-rich contact liner materialGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 19, 2016·1 cites·20 claims
- 4666US8178417B2Method of forming shallow trench isolation structures for integrated circuitsMISHRA SHAILENDRA·Filed 2008·Granted May 15, 2012·4 cites·23 claims
- 4765US8883634B2Package interconnectsYU HONG·Filed 2011·Granted Nov 11, 2014·1 cites·22 claims
- 4864US9130019B2Formation of carbon-rich contact liner materialGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 8, 2015·1 cites·20 claims
- 4959US8013372B2Integrated circuit including a stressed dielectric layer with stable stressGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Sep 6, 2011·2 cites·9 claims
- 5057US8569173B2Methods of protecting elevated polysilicon structures during etching processesLI LIANG·Filed 2011·Granted Oct 29, 2013·1 cites·12 claims
Showing the top 50 of 104 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →