Inventor · disambiguated record
Igor Keller
Also filed as: KELLER IGOR
42 granted patents·976 citations·filing 2003–2022
98Inventor score
Technology areasG06F
Top patents by PatentIndex Score
42 records- 0197US7562323B1System, method and computer program product for handling small aggressors in signal integrity analysisCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 14, 2009·208 cites·19 claims
- 0296US7882471B1Timing and signal integrity analysis of integrated circuits with semiconductor process variationsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 1, 2011·56 cites·23 claims
- 0395US7359843B1Robust calculation of crosstalk delay change in integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Apr 15, 2008·221 cites·56 claims
- 0494US10963610B1Analyzing clock jitter using delay calculation engineCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·4 cites·20 claims
- 0594US8595669B1Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Nov 26, 2013·39 cites·26 claims
- 0694US8245165B1Methods and apparatus for waveform based variational static timing analysisTIWARY SAURABH K·Filed 2008·Granted Aug 14, 2012·36 cites·20 claims
- 0792US10789406B1Characterizing electronic component parameters including on-chip variations and momentsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 29, 2020·13 cites·18 claims
- 0892US9129078B1Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stagesCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Sep 8, 2015·14 cites·15 claims
- 0992US8601420B1Equivalent waveform model for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2010·Granted Dec 3, 2013·27 cites·30 claims
- 1092US7761826B1Method and system for crosstalk analysisCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jul 20, 2010·65 cites·20 claims
- 1191US10185795B1Systems and methods for statistical static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 22, 2019·13 cites·20 claims
- 1291US10073934B1Systems and methods for statistical static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 11, 2018·13 cites·20 claims
- 1391US8543954B1Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Sep 24, 2013·28 cites·28 claims
- 1490US10275554B1Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Apr 30, 2019·10 cites·20 claims
- 1590US9881123B1Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impactCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 30, 2018·12 cites·20 claims
- 1690US8516420B1Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source modelKARIAT VINOD·Filed 2007·Granted Aug 20, 2013·19 cites·33 claims
- 1789US10430536B1Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlationCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 1, 2019·9 cites·20 claims
- 1889US9710593B1Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jul 18, 2017·10 cites·20 claims
- 1989US8341572B1Methods and apparatus for waveform based variational static timing analysisTIWARY SAURABH K·Filed 2008·Granted Dec 25, 2012·17 cites·19 claims
- 2089US8302046B1Compact modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Oct 30, 2012·20 cites·18 claims
- 2188US8966421B1Static timing analysis methods for integrated circuit designs using a multi-CCC current source modelCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 24, 2015·8 cites·8 claims
- 2288US8615725B1Methods for compact modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2012·Granted Dec 24, 2013·10 cites·23 claims
- 2387US11023636B1Methods, systems, and computer program product for characterizing an electronic design with a susceptibility windowCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jun 1, 2021·3 cites·22 claims
- 2487US8631369B1Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variationsKARIAT VINOD·Filed 2010·Granted Jan 14, 2014·10 cites·7 claims
- 2586US8782583B1Waveform based variational static timing analysisTIWARY SAURABH K·Filed 2012·Granted Jul 15, 2014·7 cites·9 claims
- 2685US9928324B1System and method for accurate modeling of back-miller effect in timing analysis of digital circuitsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 27, 2018·11 cites·20 claims
- 2785US8938703B1Method and apparatus for comprehension of common path pessimism during timing model extractionCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jan 20, 2015·10 cites·18 claims
- 2883US8104006B2Method and apparatus for thermal analysisKARIAT VINOD·Filed 2008·Granted Jan 24, 2012·13 cites·29 claims
- 2982US8375343B1Methods and apparatus for waveform based variational static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Feb 12, 2013·8 cites·20 claims
- 3081US11023640B1Methods, systems, and computer program product for characterizing timing behavior of an electronic design with a derived current waveformCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jun 1, 2021·3 cites·20 claims
- 3181US8924905B1Constructing equivalent waveform models for static timing analysis of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Dec 30, 2014·10 cites·17 claims
- 3281US8726211B2Generating an equivalent waveform model in static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted May 13, 2014·8 cites·29 claims
- 3379US11775719B1Cell instance charge model for delay calculationCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Oct 3, 2023·1 cites·20 claims
- 3478US9384310B1View data sharing for efficient multi-mode multi-corner timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jul 5, 2016·7 cites·16 claims
- 3577US9003342B1Lumped aggressor model for signal integrity timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Apr 7, 2015·7 cites·18 claims
- 3677US7464349B1Method and system or generating a current source model of a gateCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Dec 9, 2008·9 cites·14 claims
- 3775US10192012B1Pseudo-inverter configuration for signal electromigration analysisCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 29, 2019·3 cites·20 claims
- 3875US8533644B1Multi-CCC current source models and static timing analysis methods for integrated circuit designsKARIAT VINOD·Filed 2010·Granted Sep 10, 2013·3 cites·10 claims
- 3974US9582626B1Using waveform propagation for accurate delay calculationCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Feb 28, 2017·4 cites·23 claims
- 4068US11188696B1Method, system, and product for deferred merge based method for graph based analysis pessimism reductionCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Nov 30, 2021·1 cites·20 claims
- 4158US12086529B1Circuit design modification using timing-based yield calculationCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Sep 10, 2024·0 cites·20 claims
- 4258US7983891B1Receiver dependent selection of a worst-case timing event for static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jul 19, 2011·6 cites·41 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →