Inventor · disambiguated record
Injo Ok
Also filed as: OK INJO
150 granted patents·16 pending applications·520 citations·filing 2010–2023
99Inventor score
Top patents by PatentIndex Score
166 records- 0198US10741756B1Phase change memory with a patterning scheme for tantalum nitride and silicon nitride layersIBM·Filed 2019·Granted Aug 11, 2020·15 cites·20 claims
- 0298US10505111B1Confined phase change memory with double air gapIBM·Filed 2018·Granted Dec 10, 2019·37 cites·20 claims
- 0398US10297668B1Vertical transport fin field effect transistor with asymmetric channel profileIBM·Filed 2018·Granted May 21, 2019·18 cites·10 claims
- 0498US9337094B1Method of forming contact useful in replacement metal gate processing and related semiconductor structureIBM·Filed 2015·Granted May 10, 2016·38 cites·19 claims
- 0597US10115800B1Vertical fin bipolar junction transistor with high germanium content silicon germanium baseIBM·Filed 2017·Granted Oct 30, 2018·17 cites·12 claims
- 0697US9397006B1Co-integration of different fin pitches for logic and analog devicesIBM·Filed 2015·Granted Jul 19, 2016·25 cites·20 claims
- 0797US9330983B1CMOS NFET and PFET comparable spacer widthIBM·Filed 2015·Granted May 3, 2016·18 cites·15 claims
- 0896US12329045B2Phase change memory programming current leakage reductionIBM·Filed 2021·Granted Jun 10, 2025·2 cites·20 claims
- 0996US10804165B2Source and drain isolation for CMOS nanosheet with one block maskIBM·Filed 2019·Granted Oct 13, 2020·12 cites·19 claims
- 1096US10177240B2FinFET device formed by a replacement metal-gate method including a gate cut-last stepIBM·Filed 2015·Granted Jan 8, 2019·15 cites·3 claims
- 1196US9685340B2Stable contact on one-sided gate tie-down structureIBM·Filed 2015·Granted Jun 20, 2017·17 cites·17 claims
- 1296US9431486B1Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devicesIBM·Filed 2015·Granted Aug 30, 2016·13 cites·20 claims
- 1395US12010930B2Wrap-around projection liner for AI deviceIBM·Filed 2021·Granted Jun 11, 2024·2 cites·20 claims
- 1495US11456415B2Phase change memory cell with a wrap around and ring type of electrode contact and a projection linerIBM·Filed 2020·Granted Sep 27, 2022·4 cites·20 claims
- 1595US10325820B1Source and drain isolation for CMOS nanosheet with one block maskIBM·Filed 2018·Granted Jun 18, 2019·14 cites·13 claims
- 1695US9728462B2Stable multiple threshold voltage devices on replacement metal gate CMOS devicesIBM·Filed 2015·Granted Aug 8, 2017·12 cites·9 claims
- 1795US9595592B1Forming dual contact silicide using metal multi-layer and ion beam mixingIBM·Filed 2015·Granted Mar 14, 2017·11 cites·16 claims
- 1895US9305923B1Low resistance replacement metal gate structureIBM·Filed 2014·Granted Apr 5, 2016·18 cites·11 claims
- 1994US11930724B2Phase change memory cell spacerIBM·Filed 2021·Granted Mar 12, 2024·2 cites·13 claims
- 2094US10347456B1Vertical vacuum channel transistor with minimized air gap between tip and gateIBM·Filed 2018·Granted Jul 9, 2019·8 cites·16 claims
- 2194US9461168B1Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devicesIBM·Filed 2016·Granted Oct 4, 2016·8 cites·1 claims
- 2294US8183104B2Method for dual-channel nanowire FET deviceHOBBS CHRISTOPHER C·Filed 2010·Granted May 22, 2012·38 cites·15 claims
- 2393US11621394B2Multi-layer phase change memory deviceIBM·Filed 2020·Granted Apr 4, 2023·2 cites·25 claims
- 2493US10672872B1Self-aligned base contacts for vertical fin-type bipolar junction transistorsIBM·Filed 2019·Granted Jun 2, 2020·9 cites·20 claims
- 2592US10615257B2Patterning method for nanosheet transistorsIBM·Filed 2018·Granted Apr 7, 2020·7 cites·20 claims
- 2692US10396126B1Resistive memory device with electrical gate controlIBM·Filed 2018·Granted Aug 27, 2019·11 cites·20 claims
- 2792US10256296B2Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stackIBM·Filed 2015·Granted Apr 9, 2019·5 cites·11 claims
- 2892US9887289B2Method and structure of improving contact resistance for passive and long channel devicesIBM·Filed 2015·Granted Feb 6, 2018·6 cites·9 claims
- 2992US9698101B2Self-aligned local interconnect technologyIBM·Filed 2015·Granted Jul 4, 2017·6 cites·19 claims
- 3091US10381074B1Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistorsIBM·Filed 2018·Granted Aug 13, 2019·10 cites·20 claims
- 3191US9871099B2Nanosheet isolation for bulk CMOS non-planar devicesIBM·Filed 2015·Granted Jan 16, 2018·6 cites·19 claims
- 3290US11476418B2Phase change memory cell with a projection linerIBM·Filed 2020·Granted Oct 18, 2022·2 cites·14 claims
- 3390US11456417B2Integrated phase change memory cell projection liner and etch stop layerIBM·Filed 2020·Granted Sep 27, 2022·2 cites·15 claims
- 3489US10833269B13D phase change memoryIBM·Filed 2019·Granted Nov 10, 2020·5 cites·20 claims
- 3589US9704760B2Integrated circuit (IC) with offset gate sidewall contacts and method of manufactureIBM·Filed 2015·Granted Jul 11, 2017·6 cites·19 claims
- 3689US9583584B2Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methodsGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 28, 2017·6 cites·18 claims
- 3789US9520500B1Self heating reduction for analog radio frequency (RF) deviceIBM·Filed 2015·Granted Dec 13, 2016·5 cites·13 claims
- 3888US10777679B2Removal of work function metal wing to improve device yield in vertical FETsIBM·Filed 2019·Granted Sep 15, 2020·4 cites·20 claims
- 3988US10355080B2Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stackIBM·Filed 2016·Granted Jul 16, 2019·3 cites·6 claims
- 4088US9673101B2Minimize middle-of-line contact line shortsIBM·Filed 2015·Granted Jun 6, 2017·4 cites·17 claims
- 4187US10971585B2Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gatesIBM·Filed 2018·Granted Apr 6, 2021·4 cites·18 claims
- 4287US9275901B1Semiconductor device having reduced contact resistanceIBM·Filed 2014·Granted Mar 1, 2016·6 cites·10 claims
- 4386US10541329B2Boosted vertical field-effect transistorIBM·Filed 2018·Granted Jan 21, 2020·3 cites·20 claims
- 4486US10468498B2Vertical fin bipolar junction transistor with high germanium content silicon germanium baseIBM·Filed 2018·Granted Nov 5, 2019·3 cites·8 claims
- 4584US12237368B2Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stackADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Feb 25, 2025·0 cites·19 claims
- 4684US10763431B2Film stress control for memory device stackIBM·Filed 2018·Granted Sep 1, 2020·3 cites·17 claims
- 4784US10141232B2Vertical CMOS devices with common gate stacksIBM·Filed 2016·Granted Nov 27, 2018·4 cites·19 claims
- 4884US9627382B2CMOS NFET and PFET comparable spacer widthIBM·Filed 2016·Granted Apr 18, 2017·3 cites·10 claims
- 4983US10043904B2Method and structure of improving contact resistance for passive and long channel devicesIBM·Filed 2017·Granted Aug 7, 2018·2 cites·1 claims
- 5082US10832941B2Airgap isolation for backend embedded memory stack pillar arraysIBM·Filed 2019·Granted Nov 10, 2020·3 cites·14 claims
Showing the top 50 of 166 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →