Inventor · disambiguated record
James A. Culp
Also filed as: CULP JAMES · CULP JAMES A
50 granted patents·4 pending applications·392 citations·filing 2000–2024
98Inventor score
Top patents by PatentIndex Score
54 records- 0191US6713791B2T-RAM array having a planar cell structure and method for fabricating the sameIBM·Filed 2001·Granted Mar 30, 2004·48 cites·7 claims
- 0289US7865864B2Electrically driven optical proximity correctionIBM·Filed 2008·Granted Jan 4, 2011·22 cites·14 claims
- 0389US6429482B1Halo-free non-rectifying contact on chip with halo source/drain diffusionIBM·Filed 2000·Granted Aug 6, 2002·46 cites·18 claims
- 0488US7536664B2Physical design system and methodIBM·Filed 2004·Granted May 19, 2009·44 cites·18 claims
- 0587US9455186B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Sep 27, 2016·4 cites·1 claims
- 0687US7503028B2Multilayer OPC for design aware manufacturingIBM·Filed 2006·Granted Mar 10, 2009·8 cites·3 claims
- 0786US9311443B2Correcting for stress induced pattern shifts in semiconductor manufacturingGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 12, 2016·8 cites·21 claims
- 0886US8473885B2Physical design system and methodCOHN JOHN M·Filed 2012·Granted Jun 25, 2013·8 cites·20 claims
- 0986US7975244B2Methodology and system for determining numerical errors in pixel-based imaging simulation in designing lithographic masksIBM·Filed 2008·Granted Jul 5, 2011·8 cites·33 claims
- 1086US6996797B1Method for verification of resolution enhancement techniques and optical proximity correction in lithographyIBM·Filed 2004·Granted Feb 7, 2006·25 cites·20 claims
- 1185US7627836B2OPC trimming for performanceIBM·Filed 2005·Granted Dec 1, 2009·15 cites·7 claims
- 1284US8239790B2Methods and system for analysis and management of parametric yieldCULP JAMES A·Filed 2011·Granted Aug 7, 2012·4 cites·20 claims
- 1382US7565633B2Verifying mask layout printability using simulation with adjustable accuracyIBM·Filed 2007·Granted Jul 21, 2009·6 cites·3 claims
- 1481US6541166B2Method and apparatus for lithographically printing tightly nested and isolated device features using multiple mask exposuresIBM·Filed 2001·Granted Apr 1, 2003·19 cites·23 claims
- 1580US9836570B1Semiconductor layout generationGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 5, 2017·4 cites·17 claims
- 1679US9385038B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Jul 5, 2016·2 cites·6 claims
- 1778US7900178B2Integrated circuit (IC) design method, system and program productIBM·Filed 2008·Granted Mar 1, 2011·8 cites·35 claims
- 1877US9311442B2Net-voltage-aware optical proximity correction (OPC)GLOBALFOUNDRIES INC·Filed 2014·Granted Apr 12, 2016·4 cites·19 claims
- 1977US8219943B2Physical design system and methodCOHN JOHN M·Filed 2009·Granted Jul 10, 2012·6 cites·24 claims
- 2077US7890906B2Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cellsIBM·Filed 2008·Granted Feb 15, 2011·8 cites·16 claims
- 2177US7269808B2Design verificationIBM·Filed 2005·Granted Sep 11, 2007·11 cites·17 claims
- 2275US7849433B2Integrated circuit with uniform polysilicon perimeter density, method and design structureIBM·Filed 2008·Granted Dec 7, 2010·7 cites·9 claims
- 2373US8347259B1Circuit enhancement by multiplicate-layer-handling circuit simulationIBM·Filed 2011·Granted Jan 1, 2013·4 cites·25 claims
- 2473US7935638B2Methods and structures for enhancing perimeter-to-surface area homogeneityIBM·Filed 2009·Granted May 3, 2011·3 cites·12 claims
- 2572US8176444B2Analyzing multiple induced systematic and statistical layout dependent effects on circuit performanceBANERJEE SHAYAK·Filed 2009·Granted May 8, 2012·5 cites·18 claims
- 2672US7473648B2Double exposure double resist layer process for forming gate patternsIBM·Filed 2006·Granted Jan 6, 2009·5 cites·9 claims
- 2771US8214770B2Multilayer OPC for design aware manufacturingMUKHERJEE MAHARAJ·Filed 2009·Granted Jul 3, 2012·2 cites·35 claims
- 2870US6892365B2Method for performing monte-carlo simulations to predict overlay failures in integrated circuit designsIBM·Filed 2003·Granted May 10, 2005·16 cites·19 claims
- 2969US7669175B2Methodology to improve turnaround for integrated circuit design using geometrical hierarchyIBM·Filed 2007·Granted Feb 23, 2010·4 cites·8 claims
- 3068US9075106B2Detecting chip alterations with light emissionBERNSTEIN KERRY·Filed 2009·Granted Jul 7, 2015·5 cites·19 claims
- 3168US8418087B2Analyzing multiple induced systematic and statistical layout dependent effects on circuit performanceBANERJEE SHAYAK·Filed 2012·Granted Apr 9, 2013·2 cites·10 claims
- 3268US8347260B2Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverageIBM·Filed 2010·Granted Jan 1, 2013·2 cites·25 claims
- 3368US8232215B2Spacer linewidth controlCULP JAMES A·Filed 2009·Granted Jul 31, 2012·2 cites·18 claims
- 3467US9076847B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2013·Granted Jul 7, 2015·1 cites·6 claims
- 3566US9898573B2Rule and process assumption co-optimization using feature-specific layout-based statistical analysesGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 20, 2018·1 cites·20 claims
- 3666US8429576B2Methods and system for analysis and management of parametric yieldCULP JAMES A·Filed 2012·Granted Apr 23, 2013·1 cites·20 claims
- 3766US8302068B2Leakage aware design post-processingCULP JAMES A·Filed 2010·Granted Oct 30, 2012·1 cites·18 claims
- 3866US6750109B2Halo-free non-rectifying contact on chip with halo source/drain diffusionIBM·Filed 2002·Granted Jun 15, 2004·11 cites·12 claims
- 3965US8381141B2Method and system for comparing lithographic processing conditions and or data preparation processesIBM·Filed 2010·Granted Feb 19, 2013·1 cites·20 claims
- 4065US8042070B2Methods and system for analysis and management of parametric yieldIBM·Filed 2007·Granted Oct 18, 2011·3 cites·20 claims
- 4163US7805693B2IC chip design modeling using perimeter density to electrical characteristic correlationIBM·Filed 2008·Granted Sep 28, 2010·2 cites·15 claims
- 4262US8301290B2System and method for correcting systematic parametric variations on integrated circuit chips in order to minimize circuit limited yield lossCULP JAMES A·Filed 2009·Granted Oct 30, 2012·2 cites·24 claims
- 4362US8161422B2Fast and accurate method to simulate intermediate range flare effectsMUKHERJEE MAHARAJ·Filed 2009·Granted Apr 17, 2012·1 cites·18 claims
- 4458US8470713B2Nitride etch for improved spacer uniformityCULP JAMES A·Filed 2010·Granted Jun 25, 2013·1 cites·20 claims
- 4556US8997028B2Methods and system for analysis and management of parametric yieldMENTOR GRAPHICS CORP·Filed 2013·Granted Mar 31, 2015·0 cites·8 claims
- 4654US9406560B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Aug 2, 2016·0 cites·5 claims
- 4754US2025245410A1Method and system employing linear distance marker-based design layout analysisGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 4851US2024273275A1Parameterized cell with multiple layout configuration optionsGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 4950US8336008B2Characterization of long range variabilityCULP JAMES A·Filed 2009·Granted Dec 18, 2012·0 cites·23 claims
- 5048US7450748B2Mask inspection process accounting for mask writer proximity correctionIBM·Filed 2003·Granted Nov 11, 2008·2 cites·2 claims
Showing the top 50 of 54 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →