Inventor · disambiguated record
James D. Joseph
Also filed as: JOSEPH JAMES · JOSEPH JAMES D · JOSEPH JAMES DEAN
17 granted patents·596 citations·filing 1979–2008
95Inventor score
Files withACTEL CORP5HONEYWELL INC5ENHANCED MEMORY SYSTEMS INC2RAMTRON INT CORP2RAMTON INTERNATIONAL CORP1
Top patents by PatentIndex Score
17 records- 0192US6049487AEmbedded static random access memory for field programmable gate arrayACTEL CORP·Filed 1998·Granted Apr 11, 2000·91 cites·3 claims
- 0290US4468727AIntegrated cellular array parallel processorHONEYWELL INC·Filed 1981·Granted Aug 28, 1984·79 cites·67 claims
- 0385US6718477B1Delay locked loop for an FPGA architectureFiled 2000·Granted Apr 6, 2004·39 cites·4 claims
- 0480US7484113B1Delay locked loop for an FPGA architectureACTEL CORP·Filed 2006·Granted Jan 27, 2009·8 cites·6 claims
- 0579US5802560AMultibus cached memory systemRAMTON INTERNATIONAL CORP·Filed 1995·Granted Sep 1, 1998·116 cites·34 claims
- 0677US5875451AComputer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAMENHANCED MEMORY SYSTEMS INC·Filed 1996·Granted Feb 23, 1999·82 cites·23 claims
- 0776US7171575B1Delay locked loop for and FPGA architectureACTEL CORP·Filed 2005·Granted Jan 30, 2007·9 cites·7 claims
- 0870US4465940AElectro-optical target detectionUS AIR FORCE·Filed 1982·Granted Aug 14, 1984·28 cites·4 claims
- 0968US6976185B1Delay locked loop for an FPGA architectureACTEL CORP·Filed 2003·Granted Dec 13, 2005·10 cites·12 claims
- 1060US5983313AEDRAM having a dynamically-sized cache memory and associated methodRAMTRON INT CORP·Filed 1996·Granted Nov 9, 1999·43 cites·7 claims
- 1160US4553260AMeans and method of processing optical image edge dataHONEYWELL INC·Filed 1983·Granted Nov 12, 1985·30 cites·11 claims
- 1258US4754259AAngle digitizer with enhanced harmonic rejectionHONEYWELL INC·Filed 1987·Granted Jun 28, 1988·15 cites·8 claims
- 1354US7941685B2Delay locked loop for an FPGA architectureACTEL CORP·Filed 2008·Granted May 10, 2011·0 cites·10 claims
- 1448US5566318ACircuit with a single address register that augments a memory controller by enabling cache reads and page-mode writesRAMTRON INT CORP·Filed 1994·Granted Oct 15, 1996·21 cites·16 claims
- 1548US4845681AGaAs SCFL RAMHONEYWELL INC·Filed 1987·Granted Jul 4, 1989·11 cites·8 claims
- 1643US4250376AApparatus for range finding equipmentHONEYWELL INC·Filed 1979·Granted Feb 10, 1981·8 cites·11 claims
- 1731US5835442AEDRAM with integrated generation and control of write enable and column latch signals and method for making sameENHANCED MEMORY SYSTEMS INC·Filed 1996·Granted Nov 10, 1998·6 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →