Inventor · disambiguated record
Jean-Francois Cote
Also filed as: COETE JEAN-FRANCOIS · COTE JEAN-FRANCOIS · COTEJEAN-FRANCOIS
41 granted patents·5 pending applications·1,576 citations·filing 1996–2021
98Inventor score
Files withLOGICVISION INC24MENTOR GRAPHICS CORP9LOGIC VISION INC4SIEMENS IND SOFTWARE INC3MATROX GRAPHICS INC2
Top patents by PatentIndex Score
46 records- 0199US6829730B2Method of designing circuit having multiple test access ports, circuit produced thereby and method of using sameLOGICVISION INC·Filed 2001·Granted Dec 7, 2004·192 cites·51 claims
- 0297US7757135B2Method and apparatus for storing and distributing memory repair informationMENTOR GRAPHICS CORP·Filed 2007·Granted Jul 13, 2010·70 cites·23 claims
- 0396US10476740B1Data generation for streaming networks in circuitsMENTOR GRAPHICS CORP·Filed 2018·Granted Nov 12, 2019·16 cites·30 claims
- 0496US6671839B1Scan test method for providing real time identification of failing test patterns and test bist controller for use therewithLOGICVISION INC·Filed 2002·Granted Dec 30, 2003·96 cites·70 claims
- 0596US6000051AMethod and apparatus for high-speed interconnect testingLOGIC VISION INC·Filed 1997·Granted Dec 7, 1999·140 cites·43 claims
- 0694US10473721B1Data streaming for testing identical circuit blocksMENTOR GRAPHICS CORP·Filed 2018·Granted Nov 12, 2019·10 cites·28 claims
- 0794US6510534B1Method and apparatus for testing high performance circuitsLOGICVISION INC·Filed 2000·Granted Jan 21, 2003·82 cites·44 claims
- 0894US6327684B1Method of testing at-speed circuits having asynchronous clocks and controller for use therewithLOGICVISION INC·Filed 1999·Granted Dec 4, 2001·119 cites·31 claims
- 0992US6760874B2Test access circuit and method of accessing embedded test controllers in integrated circuit modulesLOGICVISION INC·Filed 2002·Granted Jul 6, 2004·54 cites·53 claims
- 1091US7370251B2Method and circuit for collecting memory failure informationLOGICVISION INC·Filed 2003·Granted May 6, 2008·55 cites·54 claims
- 1191US6952211B1Motion compensation using shared resources of a graphics processor unitMATROX GRAPHICS INC·Filed 2002·Granted Oct 4, 2005·51 cites·20 claims
- 1290US7617425B2Method for at-speed testing of memory interface using scanLOGICVISION INC·Filed 2006·Granted Nov 10, 2009·20 cites·27 claims
- 1389US11085965B2Clock gating and scan clock generation for circuit testMENTOR GRAPHICS CORP·Filed 2019·Granted Aug 10, 2021·3 cites·14 claims
- 1489US9389944B1Test access architecture for multi-die circuitsMENTOR GRAPHICS CORP·Filed 2013·Granted Jul 12, 2016·9 cites·11 claims
- 1588US6115827AClock skew management method and apparatusLOGICVISION INC·Filed 1998·Granted Sep 5, 2000·72 cites·43 claims
- 1686US9389945B1Test access architecture for stacked diesMENTOR GRAPHICS CORP·Filed 2013·Granted Jul 12, 2016·6 cites·20 claims
- 1786US7155651B2Clock controller for at-speed testing of scan circuitsLOGICVISION INC·Filed 2004·Granted Dec 26, 2006·31 cites·29 claims
- 1886US7129962B1Efficient video processing method and systemMATROX GRAPHICS INC·Filed 2002·Granted Oct 31, 2006·47 cites·20 claims
- 1986US6615392B1Hierarchical design and test method and system, program product embodying the method and integrated circuit produced therebyLOGICVISION INC·Filed 2000·Granted Sep 2, 2003·44 cites·75 claims
- 2085US6763489B2Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit descriptionLOGICVISION INC·Filed 2001·Granted Jul 13, 2004·31 cites·65 claims
- 2184US6678875B2Self-contained embedded test design environment and environment setup utilityLOGICVISION INC·Filed 2002·Granted Jan 13, 2004·40 cites·41 claims
- 2284US6536008B1Fault insertion method, boundary scan cells, and integrated circuit for use therewithLOGIC VISION INC·Filed 1998·Granted Mar 18, 2003·57 cites·76 claims
- 2384US5812469AMethod and apparatus for testing multi-port memoryLOGIC VISION INC·Filed 1996·Granted Sep 22, 1998·48 cites·4 claims
- 2481US6330681B1Method and apparatus for controlling power level during BISTLOGICVISION INC·Filed 1998·Granted Dec 11, 2001·46 cites·23 claims
- 2577US6145105AMethod and apparatus for scan testing digital circuitsLOGICVISION INC·Filed 1998·Granted Nov 7, 2000·42 cites·28 claims
- 2676US5900753AAsynchronous interfaceLOGICVISION INC·Filed 1997·Granted May 4, 1999·76 cites·67 claims
- 2774US6725435B2Method and program product for completing a circuit design having embedded test structuresLOGICVISION INC·Filed 2002·Granted Apr 20, 2004·21 cites·23 claims
- 2873US8516317B2Methods for at-speed testing of memory interfaceNADEAU-DOSTIE BENOIT·Filed 2011·Granted Aug 20, 2013·6 cites·31 claims
- 2972US6868532B2Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced therebyLOGICVISION INC·Filed 2001·Granted Mar 15, 2005·15 cites·78 claims
- 3071US6614263B2Method and circuitry for controlling clocks of embedded blocks during logic bist test modeLOGICVISION INC·Filed 2002·Granted Sep 2, 2003·14 cites·54 claims
- 3170US6738938B2Method for collecting failure information for a memory using an embedded test controllerLOGICVISION INC·Filed 2002·Granted May 18, 2004·17 cites·52 claims
- 3267US8619077B1Efficient execution of color space processing functions in a graphics processing unitCOTE JEAN-FRANCOIS·Filed 2002·Granted Dec 31, 2013·17 cites·24 claims
- 3365US10788530B1Efficient and flexible network for streaming data in circuitsMENTOR GRAPHICS CORP·Filed 2018·Granted Sep 29, 2020·0 cites·30 claims
- 3465US10775436B1Streaming networks efficiency using data throttlingMENTOR GRAPHICS CORP·Filed 2018·Granted Sep 15, 2020·0 cites·22 claims
- 3564US6046946AMethod and apparatus for testing multi-port memory using shadow readLOGIC VISION INC·Filed 1998·Granted Apr 4, 2000·19 cites·21 claims
- 3659US7424656B2Clocking methodology for at-speed testing of scan circuits with synchronous clocksLOGICVISION INC·Filed 2005·Granted Sep 9, 2008·3 cites·21 claims
- 3757US11614487B2Multi-capture at-speed scan test based on a slow clock signalSIEMENS IND SOFTWARE INC·Filed 2020·Granted Mar 28, 2023·0 cites·20 claims
- 3855US11789487B2Asynchronous interface for transporting test-related data via serial channelsSIEMENS IND SOFTWARE INC·Filed 2021·Granted Oct 17, 2023·0 cites·16 claims
- 3955US7103860B2Verification of embedded test structures in circuit designsLOGICVISION INC·Filed 2003·Granted Sep 5, 2006·7 cites·55 claims
- 4054US11042181B2Local clock injection and independent capture for circuit test of multiple cores in clock mesh architectureMENTOR GRAPHICS CORP·Filed 2019·Granted Jun 22, 2021·0 cites·17 claims
- 4143US2010037109A1Method for at-speed testing of memory interface using scanLOGICVISION INC·Filed 2009·Application pending·0 cites
- 4241US12314207B2High bandwidth IJTAG through high speed parallel busSIEMENS IND SOFTWARE INC·Filed 2021·Granted May 27, 2025·0 cites·25 claims
- 4338US2005028059A1Processor interface for test access portFiled 2004·Application pending·0 cites
- 4437US2005273683A1Insertion of embedded test in RTL to GDSII flowLOGICVISION INC·Filed 2005·Application pending·0 cites
- 4536US2005240848A1Masking circuit and method of masking corrupted bitsLOGICVISION INC·Filed 2005·Application pending·0 cites
- 4633US2003149669A1Method and system for licensing intellectual property circuitsFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →