Inventor · disambiguated record
Jerzy Tyszer
Also filed as: TYSZER JERZY
83 granted patents·2 pending applications·3,276 citations·filing 1993–2020
99Inventor score
Files withMENTOR GRAPHICS CORP39RAJSKI JANUSZ26SIEMENS IND SOFTWARE INC3MUKHERJEE NILANJAN2CZYSZ DARIUSZ1
Top patents by PatentIndex Score
85 records- 0199US7913137B2On-chip comparison and response collection tools and techniquesMENTOR GRAPHICS CORP·Filed 2007·Granted Mar 22, 2011·60 cites·5 claims
- 0299US7818644B2Multi-stage test response compactorsRAJSKI JANUSZ·Filed 2007·Granted Oct 19, 2010·65 cites·60 claims
- 0399US6829740B2Method and apparatus for selectively compacting test responsesFiled 2003·Granted Dec 7, 2004·143 cites·23 claims
- 0499US6684358B1Decompressor/PRPG for applying pseudo-random and deterministic test patternsFiled 2000·Granted Jan 27, 2004·212 cites·41 claims
- 0599US6557129B1Method and apparatus for selectively compacting test responsesFiled 2000·Granted Apr 29, 2003·237 cites·68 claims
- 0699US6543020B2Test pattern compression for an integrated circuit test environmentFiled 2001·Granted Apr 1, 2003·143 cites·27 claims
- 0799US6327687B1Test pattern compression for an integrated circuit test environmentFiled 2000·Granted Dec 4, 2001·204 cites·30 claims
- 0898US7523372B2Phase shifter with reduced linear dependencyRAJSKI JANUSZ·Filed 2007·Granted Apr 21, 2009·42 cites·21 claims
- 0998US7509546B2Test pattern compression for an integrated circuit test environmentRAJSKI JANUSZ·Filed 2006·Granted Mar 24, 2009·47 cites·21 claims
- 1098US7506232B2Decompressor/PRPG for applying pseudo-random and deterministic test patternsRAJSKI JANUSZ·Filed 2006·Granted Mar 17, 2009·47 cites·12 claims
- 1198US7111209B2Test pattern compression for an integrated circuit test environmentRAJSKI JANUSZ·Filed 2003·Granted Sep 19, 2006·92 cites·19 claims
- 1298US7093175B2Decompressor/PRPG for applying pseudo-random and deterministic test patternsRAJSKI JANUSZ·Filed 2003·Granted Aug 15, 2006·102 cites·12 claims
- 1398US5991909AParallel decompressor and related methods and apparatusesMENTOR GRAPHICS CORP·Filed 1996·Granted Nov 23, 1999·246 cites·36 claims
- 1497US7797603B2Low power decompression of test cubesRAJSKI JANUSZ·Filed 2007·Granted Sep 14, 2010·59 cites·36 claims
- 1597US7653851B2Phase shifter with reduced linear dependencyRAJSKI JANUSZ·Filed 2009·Granted Jan 26, 2010·32 cites·18 claims
- 1697US7647540B2Decompressors for low power decompression of test patternsRAJSKI JANUSZ·Filed 2007·Granted Jan 12, 2010·41 cites·24 claims
- 1797US6874109B1Phase shifter with reduced linear dependencyFiled 2000·Granted Mar 29, 2005·108 cites·47 claims
- 1896US8418007B2On-chip comparison and response collection tools and techniquesMUKHERJEE NILANJAN·Filed 2011·Granted Apr 9, 2013·12 cites·12 claims
- 1996US7925465B2Low power scan testing techniques and apparatusMENTOR GRAPHICS CORP·Filed 2008·Granted Apr 12, 2011·37 cites·48 claims
- 2096US7805649B2Method and apparatus for selectively compacting test responsesMENTOR GRAPHICS CORP·Filed 2009·Granted Sep 28, 2010·26 cites·21 claims
- 2196US7500163B2Method and apparatus for selectively compacting test responsesRAJSKI JANUSZ·Filed 2004·Granted Mar 3, 2009·60 cites·22 claims
- 2296US7260591B2Method for synthesizing linear finite state machinesRAJSKI JANUSZ·Filed 2004·Granted Aug 21, 2007·53 cites·20 claims
- 2396US6353842B1Method for synthesizing linear finite state machinesFiled 2000·Granted Mar 5, 2002·98 cites·35 claims
- 2496US5991898AArithmetic built-in self test of multiple scan-based integrated circuitsMENTOR GRAPHICS CORP·Filed 1997·Granted Nov 23, 1999·229 cites·47 claims
- 2595US9778316B2Multi-stage test response compactorsMENTOR GRAPHICS CORP·Filed 2016·Granted Oct 3, 2017·5 cites·13 claims
- 2695US7437640B2Fault diagnosis of compressed test responses having one or more unknown statesRAJSKI JANUSZ·Filed 2005·Granted Oct 14, 2008·37 cites·24 claims
- 2795US7370254B2Compressing test responses using a compactorRAJSKI JANUSZ·Filed 2004·Granted May 6, 2008·82 cites·43 claims
- 2895US6708192B2Method for synthesizing linear finite state machinesFiled 2003·Granted Mar 16, 2004·78 cites·19 claims
- 2994US8166359B2Selective per-cycle masking of scan chains for system level testRAJSKI JANUSZ·Filed 2008·Granted Apr 24, 2012·19 cites·17 claims
- 3094US7900104B2Test pattern compression for an integrated circuit test environmentMENTOR GRAPHICS CORP·Filed 2009·Granted Mar 1, 2011·17 cites·21 claims
- 3194US7302624B2Adaptive fault diagnosis of compressed test responsesRAJSKI JANUSZ·Filed 2005·Granted Nov 27, 2007·45 cites·28 claims
- 3294US7263641B2Phase shifter with reduced linear dependencyRAJSKI JANUSZ·Filed 2004·Granted Aug 28, 2007·51 cites·19 claims
- 3394US6539409B2Method for synthesizing linear finite state machinesFiled 2001·Granted Mar 25, 2003·75 cites·18 claims
- 3493US8290738B2Low power scan testing techniques and apparatusLIN XIJIANG·Filed 2011·Granted Oct 16, 2012·12 cites·31 claims
- 3593US7890827B2Compressing test responses using a compactorMENTOR GRAPHICS CORP·Filed 2010·Granted Feb 15, 2011·11 cites·15 claims
- 3693US7509550B2Fault diagnosis of compressed test responsesRAJSKI JANUSZ·Filed 2005·Granted Mar 24, 2009·36 cites·32 claims
- 3792US8914694B2On-chip comparison and response collection tools and techniquesMENTOR GRAPHICS CORP·Filed 2013·Granted Dec 16, 2014·6 cites·10 claims
- 3892US8108743B2Method and apparatus for selectively compacting test responsesRAJSKI JANUSZ·Filed 2010·Granted Jan 31, 2012·7 cites·17 claims
- 3992US8046653B2Low power decompression of test cubesMENTOR GRAPHICS CORP·Filed 2010·Granted Oct 25, 2011·10 cites·17 claims
- 4092US7865794B2Decompressor/PRPG for applying pseudo-random and deterministic test patternsMENTOR GRAPHICS CORP·Filed 2009·Granted Jan 4, 2011·14 cites·18 claims
- 4192US7478296B2Continuous application and decompression of test patterns to a circuit-under-testRAJSKI JANUSZ·Filed 2003·Granted Jan 13, 2009·46 cites·16 claims
- 4291US9250287B2On-chip comparison and response collection tools and techniquesMENTOR GRAPHICS CORP·Filed 2014·Granted Feb 2, 2016·5 cites·10 claims
- 4390US7877656B2Continuous application and decompression of test patterns to a circuit-under-testMENTOR GRAPHICS CORP·Filed 2009·Granted Jan 25, 2011·16 cites·19 claims
- 4489US7743302B2Compressing test responses using a compactorRAJSKI JANUSZ·Filed 2008·Granted Jun 22, 2010·17 cites·30 claims
- 4589US6728901B1Arithmetic built-in self-test of multiple scan-based integrated circuitsFiled 1999·Granted Apr 27, 2004·119 cites·38 claims
- 4688US11585853B2Trajectory-optimized test pattern generation for built-in self-testSIEMENS IND SOFTWARE INC·Filed 2020·Granted Feb 21, 2023·2 cites·16 claims
- 4787US9003248B2Fault-driven scan chain configuration for test-per-clockMENTOR GRAPHICS CORP·Filed 2013·Granted Apr 7, 2015·6 cites·16 claims
- 4887US8301945B2Decompressors for low power decompression of test patternsRAJSKI JANUSZ·Filed 2011·Granted Oct 30, 2012·5 cites·20 claims
- 4986US8533547B2Continuous application and decompression of test patterns and selective compaction of test responsesRAJSKI JANUSZ·Filed 2011·Granted Sep 10, 2013·6 cites·11 claims
- 5086US6954888B2Arithmetic built-in self-test of multiple scan-based integrated circuitsRAJSKI JANUSZ·Filed 2004·Granted Oct 11, 2005·34 cites·21 claims
Showing the top 50 of 85 patent records by PatentIndex Score.
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