Inventor · disambiguated record
Jose Alvin Caparas
Also filed as: CAPARAS JOSE A · CAPARAS JOSE ALVIN · CAPARAS JOSE ALVIN SANTOS
50 granted patents·548 citations·filing 2004–2019
98Inventor score
Files withSTATS CHIPPAC LTD20CAMACHO ZIGMUND RAMIREZ6ST ASSEMBLY TEST SERVICES LTD5BATHAN HENRY DESCALZO3LIN YAOJIAN3
Top patents by PatentIndex Score
50 records- 0199US7517733B2Leadframe design for QFN package with top terminal leadsSTATS CHIPPAC LTD·Filed 2007·Granted Apr 14, 2009·125 cites·22 claims
- 0298US9443797B2Semiconductor device having wire studs as vertical interconnect in FO-WLPSTATS CHIPPAC LTD·Filed 2013·Granted Sep 13, 2016·55 cites·16 claims
- 0397US8258012B2Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor diePAGAILA REZA A·Filed 2010·Granted Sep 4, 2012·25 cites·25 claims
- 0494US10453785B2Semiconductor device and method of forming double-sided fan-out wafer level packageSTATS CHIPPAC LTD·Filed 2015·Granted Oct 22, 2019·14 cites·25 claims
- 0593US8659162B2Semiconductor device having an interconnect structure with TSV using encapsulant for structural supportSUTHIWONGSUNTHORN NATHAPONG·Filed 2011·Granted Feb 25, 2014·19 cites·25 claims
- 0693US8067308B2Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural supportSUTHIWONGSUNTHORN NATHAPONG·Filed 2009·Granted Nov 29, 2011·28 cites·27 claims
- 0793US8035204B2Large die package structures and fabrication method thereforST ASSEMBLY TEST SERVICES LTD·Filed 2010·Granted Oct 11, 2011·13 cites·12 claims
- 0893US7964450B2Wirebondless wafer level package with plated bumps and interconnectsSTATS CHIPPAC LTD·Filed 2008·Granted Jun 21, 2011·22 cites·36 claims
- 0992US9293401B2Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)STATS CHIPPAC LTD·Filed 2013·Granted Mar 22, 2016·11 cites·22 claims
- 1092US8648470B2Semiconductor device and method of forming FO-WLCSP with multiple encapsulantsLIN YAOJIAN·Filed 2011·Granted Feb 11, 2014·12 cites·24 claims
- 1192US8035207B2Stackable integrated circuit package system with recessSTATS CHIPPAC LTD·Filed 2006·Granted Oct 11, 2011·23 cites·20 claims
- 1292US7443015B2Integrated circuit package system with downset leadSTATS CHIPPAC LTD·Filed 2006·Granted Oct 28, 2008·28 cites·13 claims
- 1390US10446523B2Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLPSTATS CHIPPAC PTE LTD·Filed 2016·Granted Oct 15, 2019·5 cites·25 claims
- 1490US7700404B2Large die package structures and fabrication method thereforST ASSEMBLY TEST SERVICES LTD·Filed 2006·Granted Apr 20, 2010·16 cites·16 claims
- 1586US10163747B2Semiconductor device and method of controlling warpage in reconstituted waferSTATS CHIPPAC PTE LTD·Filed 2017·Granted Dec 25, 2018·4 cites·13 claims
- 1685US7339258B2Dual row leadframe and fabrication methodST ASSEMBLY TEST SERVICES LTD·Filed 2006·Granted Mar 4, 2008·11 cites·10 claims
- 1784US9607965B2Semiconductor device and method of controlling warpage in reconstituted waferSTATS CHIPPAC LTD·Filed 2013·Granted Mar 28, 2017·6 cites·33 claims
- 1884US7129569B2Large die package structures and fabrication method thereforST ASSEMBLY TEST SERVICES LTD·Filed 2004·Granted Oct 31, 2006·28 cites·16 claims
- 1982US9054083B2Semiconductor device and method of making TSV interconnect structures using encapsulant for structural supportSTATS CHIPPAC LTD·Filed 2013·Granted Jun 9, 2015·4 cites·25 claims
- 2082US8610286B2Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSPLIN YAOJIAN·Filed 2011·Granted Dec 17, 2013·5 cites·25 claims
- 2181US9153544B2Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor dieSTATS CHIPPAC LTD·Filed 2014·Granted Oct 6, 2015·3 cites·25 claims
- 2281US8273602B2Integrated circuit package system with integration portBATHAN HENRY DESCALZO·Filed 2008·Granted Sep 25, 2012·9 cites·20 claims
- 2381US7060536B2Dual row leadframe and fabrication methodST ASSEMBLY TEST SERVICES LTD·Filed 2004·Granted Jun 13, 2006·26 cites·9 claims
- 2477US7977782B2Integrated circuit package system with dual connectivitySTATS CHIPPAC LTD·Filed 2007·Granted Jul 12, 2011·7 cites·18 claims
- 2577US7449369B2Integrated circuit package system with multiple moldingSTATS CHIPPAC LTD·Filed 2006·Granted Nov 11, 2008·6 cites·11 claims
- 2676US8502376B2Wirebondless wafer level package with plated bumps and interconnectsCAMACHO ZIGMUND R·Filed 2011·Granted Aug 6, 2013·3 cites·28 claims
- 2776US7919360B1Integrated circuit packaging system with circuitry stacking and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Apr 5, 2011·6 cites·17 claims
- 2875US8710635B2Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor diePAGAILA REZA A·Filed 2012·Granted Apr 29, 2014·2 cites·25 claims
- 2975US7960815B2Leadframe design for QFN package with top terminal leadsSTATS CHIPPAC LTD·Filed 2009·Granted Jun 14, 2011·5 cites·25 claims
- 3075US7479409B2Integrated circuit package with elevated edge leadframeSTATS CHIPPAC LTD·Filed 2006·Granted Jan 20, 2009·6 cites·20 claims
- 3171US9281259B2Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in FO-WLCSPSTATS CHIPPAC LTD·Filed 2013·Granted Mar 8, 2016·2 cites·24 claims
- 3271US9142428B2Semiconductor device and method of forming FO-WLCSP with multiple encapsulantsSTATS CHIPPAC LTD·Filed 2013·Granted Sep 22, 2015·2 cites·24 claims
- 3371US8399306B2Integrated circuit packaging system with transparent encapsulation and method of manufacture thereofKOO JUNMO·Filed 2011·Granted Mar 19, 2013·5 cites·18 claims
- 3465US8455988B2Integrated circuit package system with bumped lead and nonbumped leadCAPARAS JOSE ALVIN·Filed 2008·Granted Jun 4, 2013·4 cites·20 claims
- 3565US7998790B2Integrated circuit packaging system with isolated pads and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Aug 16, 2011·2 cites·9 claims
- 3663US8258609B2Integrated circuit package system with lead supportCAMACHO ZIGMUND RAMIREZ·Filed 2007·Granted Sep 4, 2012·2 cites·18 claims
- 3761US8698294B2Integrated circuit package system including wide flange leadframeCAMACHO ZIGMUND RAMIREZ·Filed 2006·Granted Apr 15, 2014·2 cites·8 claims
- 3858US8207600B2Integrated circuit package system with encapsulating featuresBATHAN HENRY DESCALZO·Filed 2007·Granted Jun 26, 2012·1 cites·20 claims
- 3957US11127668B2Semiconductor device and method of forming double-sided fan-out wafer level packageJCET SEMICONDUCTOR SHAOXING CO LTD·Filed 2019·Granted Sep 21, 2021·0 cites·24 claims
- 4054US7871863B2Integrated circuit package system with multiple moldingSTATS CHIPPAC LTD·Filed 2008·Granted Jan 18, 2011·0 cites·12 claims
- 4153US8269324B2Integrated circuit package system with chip on leadARNEL SENOSA TRASPORTO·Filed 2008·Granted Sep 18, 2012·1 cites·20 claims
- 4252US10297556B2Semiconductor device and method of controlling warpage in reconstituted waferSTATS CHIPPAC PTE LTD·Filed 2017·Granted May 21, 2019·0 cites·26 claims
- 4351US10622293B2Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLB-MLP)JCET SEMICONDUCTOR SHAOXING CO LTD·Filed 2016·Granted Apr 14, 2020·0 cites·25 claims
- 4451US8389332B2Integrated circuit packaging system with isolated pads and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2011·Granted Mar 5, 2013·0 cites·18 claims
- 4550US9076737B2Integrated circuit packaging system with bumps and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2009·Granted Jul 7, 2015·0 cites·10 claims
- 4650US8252634B2Integrated circuit packaging system with a leadframe having radial-segments and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2009·Granted Aug 28, 2012·0 cites·20 claims
- 4748US8664038B2Integrated circuit packaging system with stacked paddle and method of manufacture thereofCAMACHO ZIGMUND RAMIREZ·Filed 2008·Granted Mar 4, 2014·0 cites·13 claims
- 4848US8569872B2Integrated circuit package system with lead-frame paddle scheme for single axis partial saw isolationBATHAN HENRY DESCALZO·Filed 2008·Granted Oct 29, 2013·0 cites·20 claims
- 4947US9059157B2Integrated circuit packaging system with substrate and method of manufacture thereofLIN YAOJIAN·Filed 2013·Granted Jun 16, 2015·0 cites·20 claims
- 5043US7482683B2Integrated circuit encapsulation system with ventSTATS CHIPPAC LTD·Filed 2006·Granted Jan 27, 2009·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →