Inventor · disambiguated record
Joe Lee
Also filed as: LEE JOE
35 granted patents·5 pending applications·271 citations·filing 2004–2024
97Inventor score
Top patents by PatentIndex Score
40 records- 0198US10020254B1Integration of super via structure in BEOLIBM·Filed 2017·Granted Jul 10, 2018·39 cites·8 claims
- 0298US10020255B1Integration of super via structure in BEOLIBM·Filed 2017·Granted Jul 10, 2018·36 cites·12 claims
- 0398US9953865B1Structure and method to improve FAV RIE process margin and electromigrationIBM·Filed 2016·Granted Apr 24, 2018·23 cites·20 claims
- 0498US9349687B1Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnectIBM·Filed 2015·Granted May 24, 2016·96 cites·20 claims
- 0596US9373582B1Self aligned via in integrated circuitIBM·Filed 2015·Granted Jun 21, 2016·18 cites·8 claims
- 0694US9385078B1Self aligned via in integrated circuitIBM·Filed 2016·Granted Jul 5, 2016·11 cites·1 claims
- 0793US10622301B2Method of forming a straight via profile with precise critical dimension controlIBM·Filed 2018·Granted Apr 14, 2020·8 cites·15 claims
- 0891US11837501B2Selective recessing to form a fully aligned viaADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Dec 5, 2023·1 cites·26 claims
- 0990US2025140611A1Selective recessing to form a fully aligned viaADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 1089US9390967B2Method for residue-free block pattern transfer onto metal interconnects for air gap formationIBM·Filed 2014·Granted Jul 12, 2016·9 cites·19 claims
- 1187US11710658B2Structure and method to improve FAV RIE process margin and ElectromigrationTESSERA LLC·Filed 2021·Granted Jul 25, 2023·1 cites·18 claims
- 1287US10312434B2Selective deposition and nitridization of bottom electrode metal for MRAM applicationsIBM·Filed 2017·Granted Jun 4, 2019·4 cites·14 claims
- 1386US2025132199A1Structure and method to improve fav rie process margin and electromigrationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 1485US10672705B2Method of forming a straight via profile with precise critical dimension controlIBM·Filed 2019·Granted Jun 2, 2020·3 cites·16 claims
- 1585US10049974B2Metal silicate spacers for fully aligned viasIBM·Filed 2016·Granted Aug 14, 2018·4 cites·13 claims
- 1684US10347825B2Selective deposition and nitridization of bottom electrode metal for MRAM applicationsIBM·Filed 2017·Granted Jul 9, 2019·3 cites·14 claims
- 1783US12033892B2Structure and method to improve FAV RIE process margin and electromigrationTESSERA LLC·Filed 2023·Granted Jul 9, 2024·0 cites·19 claims
- 1883US10985056B2Structure and method to improve FAV RIE process margin and ElectromigrationTESSERA INC·Filed 2017·Granted Apr 20, 2021·2 cites·4 claims
- 1982US12183634B2Selective recessing to form a fully aligned viaADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Dec 31, 2024·0 cites·22 claims
- 2082US10276436B2Selective recessing to form a fully aligned viaIBM·Filed 2016·Granted Apr 30, 2019·2 cites·9 claims
- 2180US10121676B2Interconnects fabricated by hydrofluorocarbon gas-assisted plasma etchIBM·Filed 2017·Granted Nov 6, 2018·2 cites·19 claims
- 2280US9905513B1Selective blocking boundary placement for circuit locations requiring electromigration short-lengthIBM·Filed 2016·Granted Feb 27, 2018·2 cites·10 claims
- 2377US11037822B2Svia using a single damascene interconnectIBM·Filed 2019·Granted Jun 15, 2021·2 cites·16 claims
- 2476US10957584B2Structure and method to improve FAV RIE process margin and electromigrationTESSERA INC·Filed 2017·Granted Mar 23, 2021·1 cites·5 claims
- 2575US11257717B2Selective recessing to form a fully aligned viaTESSERA INC·Filed 2020·Granted Feb 22, 2022·0 cites·27 claims
- 2675US9252051B1Method for top oxide rounding with protection of patterned featuresIBM·Filed 2014·Granted Feb 2, 2016·3 cites·20 claims
- 2769US12266607B2Bottom barrier free interconnects without voidsIBM·Filed 2021·Granted Apr 1, 2025·0 cites·18 claims
- 2867US9768113B2Self aligned via in integrated circuitIBM·Filed 2016·Granted Sep 19, 2017·1 cites·11 claims
- 2964US10636706B2Selective recessing to form a fully aligned viaTESSERA INC·Filed 2018·Granted Apr 28, 2020·0 cites·20 claims
- 3063US12400859B2Metal hard mask for precise tuning of mandrelsIBM·Filed 2022·Granted Aug 26, 2025·0 cites·25 claims
- 3163US10832952B2Selective recessing to form a fully aligned viaTESSERA INC·Filed 2018·Granted Nov 10, 2020·0 cites·20 claims
- 3262US11164815B2Bottom barrier free interconnects without voidsIBM·Filed 2019·Granted Nov 2, 2021·0 cites·15 claims
- 3361US10643859B2Hydrofluorocarbon gas-assisted plasma etch for interconnect fabricationIBM·Filed 2018·Granted May 5, 2020·0 cites·17 claims
- 3457US10170416B2Selective blocking boundary placement for circuit locations requiring electromigration short-lengthIBM·Filed 2017·Granted Jan 1, 2019·0 cites·19 claims
- 3556US10211138B2Metal silicate spacers for fully aligned viasIBM·Filed 2018·Granted Feb 19, 2019·0 cites·20 claims
- 3655US2025174549A1Svia formation using vftl schemeIBM·Filed 2023·Application pending·0 cites
- 3752US9934984B2Hydrofluorocarbon gas-assisted plasma etch for interconnect fabricationIBM·Filed 2015·Granted Apr 3, 2018·0 cites·17 claims
- 3849US11721578B2Split ash processes for via formation to suppress damage to low-K layersTOKYO ELECTRON LTD·Filed 2020·Granted Aug 8, 2023·0 cites·15 claims
- 3949US2005227046A1Glass shard-paved structureLEE JOE·Filed 2004·Application pending·0 cites
- 4041US2005199009A1Method for recyling glassFiled 2004·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Joe Lee files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →