Inventor · disambiguated record
Juergen Boemmels
Also filed as: BOEMMELS JUERGEN
29 granted patents·7 pending applications·186 citations·filing 2007–2025
94Inventor score
Top patents by PatentIndex Score
36 records- 0198US8048811B2Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric materialADVANCED MICRO DEVICES INC·Filed 2009·Granted Nov 1, 2011·153 cites·24 claims
- 0293US11515399B2Self-aligned contacts for walled nanosheet and forksheet field effect transistor devicesIMEC VZW·Filed 2020·Granted Nov 29, 2022·3 cites·18 claims
- 0391US11244949B2Semiconductor device having stacked transistor pairs and method of forming sameIMEC VZW·Filed 2019·Granted Feb 8, 2022·9 cites·15 claims
- 0487US10242907B2Method for interrupting a line in an interconnectIMEC VZW·Filed 2017·Granted Mar 26, 2019·5 cites·10 claims
- 0578US9859161B2Self-aligned interconnectsIMEC VZW·Filed 2017·Granted Jan 2, 2018·3 cites·16 claims
- 0669US10566236B2Method of forming vertical channel devicesIMEC VZW·Filed 2018·Granted Feb 18, 2020·1 cites·11 claims
- 0767US8039398B2Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devicesGLOBALFOUNDRIES INC·Filed 2007·Granted Oct 18, 2011·2 cites·22 claims
- 0866US11677401B23D integrated countIMEC VZW·Filed 2022·Granted Jun 13, 2023·0 cites·16 claims
- 0965US8198190B2Semiconductor device and method for patterning vertical contacts and metal lines in a common etch processRICHTER RALF·Filed 2008·Granted Jun 12, 2012·3 cites·16 claims
- 1064US8404577B2Semiconductor device having a grain orientation layerBOEMMELS JUERGEN·Filed 2008·Granted Mar 26, 2013·3 cites·10 claims
- 1162US11381242B23D integrated circuitIMEC VZW·Filed 2020·Granted Jul 5, 2022·0 cites·10 claims
- 1262US7767593B2Semiconductor device including field effect transistors laterally enclosed by interlayer dielectric material having increased intrinsic stressADVANCED MICRO DEVICES INC·Filed 2008·Granted Aug 3, 2010·1 cites·22 claims
- 1362US2025212494A1Method for Forming a Semiconductor StructureIMEC VZW·Filed 2024·Application pending·0 cites
- 1462US2025212504A1Method for Producing Nanosheet TransistorsIMEC VZW·Filed 2024·Application pending·0 cites
- 1560US2024266349A1Cfet cell architecture with a side-routing structureIMEC VZW·Filed 2024·Application pending·0 cites
- 1658US8658494B2Dual contact metallization including electroless plating in a semiconductor deviceFROHBERG KAI·Filed 2010·Granted Feb 25, 2014·1 cites·18 claims
- 1756US11488826B2Self-aligned layer patterningIMEC VZW·Filed 2020·Granted Nov 1, 2022·0 cites·12 claims
- 1855US8097536B2Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layerSCHUEHRER HOLGER·Filed 2009·Granted Jan 17, 2012·2 cites·14 claims
- 1953US2023197525A1Method for Forming a Semiconductor Device StructureIMEC VZW·Filed 2022·Application pending·0 cites
- 2053US2025311411A1CFET Structure and Method of Fabricating a CFET StructureIMEC VZW·Filed 2025·Application pending·0 cites
- 2150US2025280606A1Method for Forming a Semiconductor Device, and a Semiconductor DeviceIMEC VZW·Filed 2025·Application pending·0 cites
- 2249US7781329B2Reducing leakage in dielectric materials including metal regions including a metal cap layer in semiconductor devicesADVANCED MICRO DEVICES INC·Filed 2009·Granted Aug 24, 2010·0 cites·24 claims
- 2348US11682591B2Method for forming transistor structuresIMEC VZW·Filed 2021·Granted Jun 20, 2023·0 cites·10 claims
- 2448US11462443B2Self-aligned contacts for nanosheet field effect transistor devicesIMEC VZW·Filed 2020·Granted Oct 4, 2022·0 cites·18 claims
- 2548US10748815B2Three-dimensional semiconductor device and method of manufacturing sameIMEC VZW·Filed 2019·Granted Aug 18, 2020·0 cites·15 claims
- 2647US11295977B2Standard cell device and method of forming an interconnect structure for a standard cell deviceIMEC VZW·Filed 2020·Granted Apr 5, 2022·0 cites·13 claims
- 2747US8741770B2Semiconductor device and method for patterning vertical contacts and metal lines in a common etch processRICHTER RALF·Filed 2012·Granted Jun 3, 2014·0 cites·4 claims
- 2845US11127627B2Method for forming an interconnection structureIMEC VZW·Filed 2019·Granted Sep 21, 2021·0 cites·10 claims
- 2944US10546930B2Method of forming vertical channel devicesIMEC VZW·Filed 2018·Granted Jan 28, 2020·0 cites·14 claims
- 3042US10763159B2Method for forming a multi-level interconnect structureIMEC VZW·Filed 2019·Granted Sep 1, 2020·0 cites·11 claims
- 3142US10374084B2Vertical channel devices and method of fabricating sameIMEC VZW·Filed 2018·Granted Aug 6, 2019·0 cites·14 claims
- 3241US11257823B2Semiconductor device having vertical transistors and method of forming sameIMEC VZW·Filed 2018·Granted Feb 22, 2022·0 cites·11 claims
- 3340US10847415B2Self-aligned gate contactIMEC VZW·Filed 2017·Granted Nov 24, 2020·0 cites·13 claims
- 3440US10395978B2Method of patterning target layerIMEC VZW·Filed 2018·Granted Aug 27, 2019·0 cites·18 claims
- 3540US2009085173A1Sidewall protection layerBOEMMELS JUERGEN·Filed 2008·Application pending·0 cites
- 3638US10833161B2Semiconductor device and methodIMEC VZW·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →