Inventor · disambiguated record
Kaushik Chanda
Also filed as: CHANDA KAUSHIK
54 granted patents·10 pending applications·537 citations·filing 2001–2021
98Inventor score
Top patents by PatentIndex Score
64 records- 0199US7397260B2Structure and method for monitoring stress-induced degradation of conductive interconnectsIBM·Filed 2005·Granted Jul 8, 2008·169 cites·12 claims
- 0295US9935052B1Power line layout in integrated circuitsALTERA CORP·Filed 2014·Granted Apr 3, 2018·21 cites·16 claims
- 0394US8633707B2Stacked via structure for metal fuse applicationsFILIPPI RONALD G·Filed 2011·Granted Jan 21, 2014·15 cites·17 claims
- 0493US9685404B2Back-end electrically programmable fuseBAO JUNJING·Filed 2012·Granted Jun 20, 2017·14 cites·11 claims
- 0593US8232646B2Interconnect structure for integrated circuits having enhanced electromigration resistanceBONILLA GRISELDA·Filed 2010·Granted Jul 31, 2012·17 cites·15 claims
- 0693US7745282B2Interconnect structure with bi-layer metal capIBM·Filed 2007·Granted Jun 29, 2010·26 cites·10 claims
- 0792US7314786B1Metal resistor, resistor material and methodIBM·Filed 2006·Granted Jan 1, 2008·18 cites·5 claims
- 0891US8056039B2Interconnect structure for integrated circuits having improved electromigration characteristicsIBM·Filed 2008·Granted Nov 8, 2011·23 cites·17 claims
- 0991US7749778B2Addressable hierarchical metal wire test methodologyIBM·Filed 2007·Granted Jul 6, 2010·17 cites·1 claims
- 1090US8120179B2Air gap interconnect structures and methods for forming the sameCHANDA KAUSHIK·Filed 2009·Granted Feb 21, 2012·19 cites·18 claims
- 1188US10048306B1Methods and apparatus for automated integrated circuit package testingALTERA CORP·Filed 2015·Granted Aug 14, 2018·12 cites·9 claims
- 1288US8383507B2Method for fabricating air gap interconnect structuresIBM·Filed 2012·Granted Feb 26, 2013·8 cites·19 claims
- 1387US9142506B2E-fuse structures and methods of manufactureIBM·Filed 2013·Granted Sep 22, 2015·7 cites·11 claims
- 1487US6784105B1Simultaneous native oxide removal and metal neutral deposition methodINFINEON TECHNOLOGIES CORP·Filed 2003·Granted Aug 31, 2004·45 cites·16 claims
- 1585US8962467B2Metal fuse structure for improved programming capabilityBONILLA GRISELDA·Filed 2012·Granted Feb 24, 2015·6 cites·9 claims
- 1685US8232645B2Interconnect structures, design structure and method of manufactureYANG CHIH-CHAO·Filed 2008·Granted Jul 31, 2012·9 cites·14 claims
- 1784US7737528B2Structure and method of forming electrically blown metal fuses for integrated circuitsIBM·Filed 2008·Granted Jun 15, 2010·12 cites·20 claims
- 1884US7563704B2Method of forming an interconnect including a dielectric cap having a tensile stressIBM·Filed 2005·Granted Jul 21, 2009·12 cites·14 claims
- 1982US8420537B2Stress locking layer for reliable metallizationCHANDA KAUSHIK·Filed 2008·Granted Apr 16, 2013·11 cites·11 claims
- 2080US8742766B2Stacked via structure for metal fuse applicationsIBM·Filed 2013·Granted Jun 3, 2014·3 cites·3 claims
- 2179US7830019B2Via bottom contact and method of manufacturing sameIBM·Filed 2009·Granted Nov 9, 2010·7 cites·20 claims
- 2279US7671362B2Test structure for determining optimal seed and liner layer thicknesses for dual damascene processingIBM·Filed 2007·Granted Mar 2, 2010·6 cites·7 claims
- 2378US8610276B2Metal cap for back end of line (BEOL) interconnects, design structure and method of manufactureYANG CHIH-CHAO·Filed 2012·Granted Dec 17, 2013·3 cites·11 claims
- 2477US9425144B2Metal fuse structure for improved programming capabilityGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 23, 2016·3 cites·15 claims
- 2576US9893011B2Back-end electrically programmable fuseIBM·Filed 2015·Granted Feb 13, 2018·2 cites·4 claims
- 2676US7732924B2Semiconductor wiring structures including dielectric cap within metal cap layerIBM·Filed 2007·Granted Jun 8, 2010·6 cites·7 claims
- 2773US7776737B2Reliability of wide interconnectsIBM·Filed 2008·Granted Aug 17, 2010·5 cites·25 claims
- 2872US7683651B2Test structure for electromigration analysis and related methodIBM·Filed 2009·Granted Mar 23, 2010·5 cites·15 claims
- 2972US7521952B2Test structure for electromigration analysis and related methodIBM·Filed 2007·Granted Apr 21, 2009·5 cites·2 claims
- 3072US7287325B2Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishingIBM·Filed 2005·Granted Oct 30, 2007·3 cites·7 claims
- 3171US9673089B2Interconnect structure with enhanced reliabilityIBM·Filed 2014·Granted Jun 6, 2017·2 cites·20 claims
- 3271US7955971B2Hybrid metallic wire and methods of fabricating sameIBM·Filed 2009·Granted Jun 7, 2011·4 cites·30 claims
- 3370US7639032B2Structure for monitoring stress-induced degradation of conductive interconnectsIBM·Filed 2007·Granted Dec 29, 2009·2 cites·7 claims
- 3469US8053257B2Method for prediction of premature dielectric breakdown in a semiconductorIBM·Filed 2008·Granted Nov 8, 2011·5 cites·11 claims
- 3568US8836124B2Fuse and integrated conductorBONILLA GRISELDA·Filed 2012·Granted Sep 16, 2014·2 cites·13 claims
- 3667US8912658B2Interconnect structure with enhanced reliabilityFILIPPI RONALD·Filed 2010·Granted Dec 16, 2014·2 cites·12 claims
- 3764US8298948B2Capping of copper interconnect lines in integrated circuit devicesBONILLA GRISELDA·Filed 2009·Granted Oct 30, 2012·2 cites·20 claims
- 3864US8003474B2Electrically programmable fuse and fabrication methodIBM·Filed 2008·Granted Aug 23, 2011·2 cites·9 claims
- 3963US7585764B2VIA bottom contact and method of manufacturing sameIBM·Filed 2005·Granted Sep 8, 2009·2 cites·16 claims
- 4058US9360525B2Stacked via structure for metal fuse applicationsIBM·Filed 2014·Granted Jun 7, 2016·0 cites·20 claims
- 4157US7692439B2Structure for modeling stress-induced degradation of conductive interconnectsIBM·Filed 2008·Granted Apr 6, 2010·0 cites·6 claims
- 4257US7202159B2Diffusion barriers comprising a self-assembled monolayerRENSSELAER POLYTECH INST·Filed 2004·Granted Apr 10, 2007·5 cites·14 claims
- 4356US10229875B2Stacked via structure for metal fuse applicationsIBM·Filed 2016·Granted Mar 12, 2019·0 cites·20 claims
- 4456US8716071B2Methods and systems involving electrically reprogrammable fusesIBM·Filed 2013·Granted May 6, 2014·0 cites·4 claims
- 4555US12417331B2Systems and methods for circuit design dependent programmable maximum junction temperaturesINTEL CORP·Filed 2021·Granted Sep 16, 2025·0 cites·20 claims
- 4654US8563419B2Method of manufacturing an interconnect structure and design structure thereofYANG CHIH-CHAO·Filed 2012·Granted Oct 22, 2013·0 cites·15 claims
- 4753US7479869B2Metal resistor and resistor materialIBM·Filed 2007·Granted Jan 20, 2009·0 cites·3 claims
- 4853US2009045484A1Methods and systems involving electrically reprogrammable fusesIBM·Filed 2007·Application pending·0 cites
- 4950US9059169B2E-fuse structures and methods of manufactureBONILLA GRISELDA·Filed 2011·Granted Jun 16, 2015·0 cites·18 claims
- 5050US8535991B2Methods and systems involving electrically reprogrammable fusesCHANDA KAUSHIK·Filed 2010·Granted Sep 17, 2013·0 cites·8 claims
Showing the top 50 of 64 patent records by PatentIndex Score.
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