Inventor · disambiguated record
Kah Wee Gan
Also filed as: GAN KAH W · GAN KAH WEE
12 granted patents·7 pending applications·94 citations·filing 2005–2023
88Inventor score
Files withGLOBALFOUNDRIES SG PTE LTD8GAN KAH WEE7HWANG HOW YUAN1JIN YONGGANG1ST MICROELECTRONICS PTE LTD1
Top patents by PatentIndex Score
19 records- 0194US8779601B2Embedded wafer level package for 3D and package-on-package applications, and method of manufactureGAN KAH WEE·Filed 2011·Granted Jul 15, 2014·34 cites·10 claims
- 0293US8916481B2Embedded wafer level package for 3D and package-on-package applications, and method of manufactureGAN KAH WEE·Filed 2011·Granted Dec 23, 2014·33 cites·25 claims
- 0388US10468457B1Magnetic random access memory structures and integrated circuits with cobalt anti-parallel layers, and methods for fabricating the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Nov 5, 2019·9 cites·20 claims
- 0482US8617987B2Through hole via filling using electroless platingGAN KAH WEE·Filed 2010·Granted Dec 31, 2013·7 cites·9 claims
- 0572US8922013B2Through via packageHWANG HOW YUAN·Filed 2011·Granted Dec 30, 2014·5 cites·13 claims
- 0670US8766422B2Through hole via filling using electroless platingGAN KAH WEE·Filed 2011·Granted Jul 1, 2014·3 cites·3 claims
- 0766US9318459B2Through via packageST MICROELECTRONICS PTE LTD·Filed 2014·Granted Apr 19, 2016·2 cites·12 claims
- 0861US8728831B2Reconstituted wafer warpage adjustmentGAN KAH WEE·Filed 2010·Granted May 20, 2014·1 cites·15 claims
- 0956US11742283B2Integrated thin film resistor and memory deviceGLOBALFOUNDRIES SG PTE LTD·Filed 2020·Granted Aug 29, 2023·0 cites·19 claims
- 1055US11335635B2Thin film resistors of semiconductor devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2020·Granted May 17, 2022·0 cites·20 claims
- 1151US2024413162A1Cavity with bottom having dielectric layer portion over gate body without etch stop layer and related methodGLOBALFOUNDRIES SG PTE LTD·Filed 2023·Application pending·0 cites
- 1248US9842989B2Magnetic memory with high thermal budgetGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Dec 12, 2017·0 cites·20 claims
- 1339US2021028349A1Integrated circuits with magnetic tunnel junction memory cells and methods for producing the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Application pending·0 cites
- 1438US8912653B2Plasma treatment on semiconductor wafersGAN KAH WEE·Filed 2011·Granted Dec 16, 2014·0 cites·13 claims
- 1536US2016276580A1Bottom electrode for magnetic memory to increase tmr and thermal budgetGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Application pending·0 cites
- 1636US2018233661A1Device alignment mark using a planarization processGLOBALFOUNDRIES SG PTE LTD·Filed 2017·Application pending·0 cites
- 1735US2012168943A1Plasma treatment on semiconductor wafersGAN KAH WEE·Filed 2010·Application pending·0 cites
- 1835US2012282767A1Method for producing a two-sided fan-out wafer level package with electrically conductive interconnects, and a corresponding semiconductor packageJIN YONGGANG·Filed 2011·Application pending·0 cites
- 1934US2006160267A1Under bump metallurgy in integrated circuitsSTATS CHIPPAC LTD·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →