Inventor · disambiguated record
Kevin Lyne
Also filed as: LYNE KEVIN · LYNE KEVIN P · LYNE KEVIN PETER
7 granted patents·8 pending applications·208 citations·filing 1999–2015
85Inventor score
Top patents by PatentIndex Score
15 records- 0195US8957525B23D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processorTEXAS INSTRUMENTS INC·Filed 2012·Granted Feb 17, 2015·27 cites·13 claims
- 0287US6285560B1Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modifiedTEXAS INSTRUMENTS INC·Filed 1999·Granted Sep 4, 2001·107 cites·25 claims
- 0381US6689634B1Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliabilityTEXAS INSTRUMENTS INC·Filed 1999·Granted Feb 10, 2004·67 cites·31 claims
- 0466US8053349B2BGA package with traces for plating pads under the chipTEXAS INSTRUMENTS INC·Filed 2008·Granted Nov 8, 2011·3 cites·13 claims
- 0561US7449364B2Device and method for including passive components in a chip scale packageTEXAS INSTRUMENTS INC·Filed 2006·Granted Nov 11, 2008·2 cites·7 claims
- 0651US2010038764A1Package on Package Design a Combination of Laminate and Tape Substrate with Back-to-Back Die CombinationTEXAS INSTRUMENTS INC·Filed 2009·Application pending·0 cites
- 0746US9312253B2Heterogeneous integration of memory and split-architecture processorTEXAS INSTRUMENTS INC·Filed 2015·Granted Apr 12, 2016·0 cites·13 claims
- 0846US2007187836A1Package on package design a combination of laminate and tape substrate, with back-to-back die combinationTEXAS INSTRUMENTS INC·Filed 2006·Application pending·0 cites
- 0945US7105923B2Device and method for including passive components in a chip scale packageTEXAS INSTRUMENTS INC·Filed 2002·Granted Sep 12, 2006·2 cites·8 claims
- 1043US2008258285A1Simplified Substrates for Semiconductor Devices in Package-on-Package ProductsTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 1142US2008153265A1Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a WaferTEXAS INSTRUMENTS INC·Filed 2006·Application pending·0 cites
- 1240US2012013003A1Bga package with traces for plating pads under the chipRHYNER KENNETH R·Filed 2011·Application pending·0 cites
- 1340US2007187818A1Package on package design a combination of laminate and tape substrateTEXAS INSTRUMENTS INC·Filed 2006·Application pending·0 cites
- 1439US2007029661A1Power plane design and jumper wire bond for voltage drop minimizationTEXAS INSTRUMENTS INC·Filed 2005·Application pending·0 cites
- 1534US2011193200A1Semiconductor wafer chip scale package test flow and dicing processLYNE KEVIN P·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →