Bga package with traces for plating pads under the chip

Abstract

A semiconductor flip-chip ball grid array package with one-metal-layered substrate. The sites of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area, when the sites can be routed for metal plating. The space to place a maximum number of signal routing traces is opened up by interrupting the periodicity of the site array from the edge of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.

1 . An electronic device comprising:
 a semiconductor chip having metal bumps on chip contacts;   an insulating substrate with a central region surrounded by peripheral regions, the substrate having a first surface and a second surface, edges, and a patterned metal foil on the first surface;   the substrate further including conductive vias extending from the first to the second surface, the vias populating a first group of selected sites and a second group of selected sites;   the first set of selected sites being in the central region forming a first two-dimensional array of a first pitch and with vias located at array sites; the second set of selected sites being in the peripheral regions forming a second two-dimensional array of a second pitch with vias located at array sites;   free-zones in the first array and in the second array, each defined by a cluster of adjacent array sites free of vias;   the metal foil pattern including lands disposed over the vias; and traces connecting lands to the substrate edges;   a plurality of traces disposed in the free-zones between at least two adjacent pair of vias of the second array of vias, where the at least two adjacent pair of vias are spaced multiple first pitches apart from each other;   trace pads on the first surface matching the chip contacts; and   the semiconductor chip attached to the central substrate region with the metal bumps contacting the trace pads.   
     
     
         2 . The device of  claim 1  further including solder bodies on the second substrate surface, the solder bodies attached to the conductive vias. 
     
     
         3 . The device of  claim 1 , wherein the free-zones are oriented parallel to the traces located therein. 
     
     
         4 . The device of  claim 1  wherein a free-zone in a peripheral substrate region is aligned with a free-zone in the central region. 
     
     
         5 . The device of  claim 1  wherein the traces are connected to the electroplating bar. 
     
     
         6 . The device of  claim 1  wherein the substrate is free of conductive metal between the first surface and the second surface except the conductive metal in the vias.