Inventor · disambiguated record
King-Ho Tam
Also filed as: TAM KING-HO
34 granted patents·8 pending applications·302 citations·filing 2007–2025
96Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD22GLOBAL UNICHIP CORP5KELLER IGOR4TAIWAN SEMICONDUCTOR MFG3CADENCE DESIGN SYSTEMS INC2
Top patents by PatentIndex Score
42 records- 0197US8826212B2Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formedTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 2, 2014·112 cites·20 claims
- 0294US8595669B1Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Nov 26, 2013·39 cites·26 claims
- 0392US12113051B2Die to die interface circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Oct 8, 2024·1 cites·18 claims
- 0492US9129078B1Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stagesCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Sep 8, 2015·14 cites·15 claims
- 0591US8694945B2Automatic place and route method for electromigration tolerant power distributionWANG CHUNG-HSING·Filed 2011·Granted Apr 8, 2014·13 cites·13 claims
- 0691US8543954B1Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Sep 24, 2013·28 cites·28 claims
- 0790US11620426B2Automated system and method for circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Apr 4, 2023·2 cites·20 claims
- 0890US8516420B1Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source modelKARIAT VINOD·Filed 2007·Granted Aug 20, 2013·19 cites·33 claims
- 0989US8302046B1Compact modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Oct 30, 2012·20 cites·18 claims
- 1088US12001773B2Automated system and method for circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 4, 2024·1 cites·20 claims
- 1188US9477803B2Method of generating techfile having reduced corner variation valueTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Oct 25, 2016·9 cites·20 claims
- 1288US8966421B1Static timing analysis methods for integrated circuit designs using a multi-CCC current source modelCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 24, 2015·8 cites·8 claims
- 1388US8615725B1Methods for compact modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2012·Granted Dec 24, 2013·10 cites·23 claims
- 1487US11031923B1Interface device and interface method for 3D semiconductor deviceGLOBAL UNICHIP CORP·Filed 2020·Granted Jun 8, 2021·2 cites·20 claims
- 1585US11658158B2Die to die interface circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted May 23, 2023·1 cites·20 claims
- 1684US2025363274A1Integrated circuit design system, method and computer program productTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1783US9058462B2System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE)TAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jun 16, 2015·7 cites·20 claims
- 1879US12367333B2Automated system and method for circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 1978US2024387471A1Die to die interface circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2077US2025232101A1Integrated circuit design system, method and computer program productTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2175US8533644B1Multi-CCC current source models and static timing analysis methods for integrated circuit designsKARIAT VINOD·Filed 2010·Granted Sep 10, 2013·3 cites·10 claims
- 2274US9311440B2System and method of electromigration avoidance for automatic place-and-routeKAO JERRY·Filed 2012·Granted Apr 12, 2016·5 cites·20 claims
- 2371US9563734B2Characterizing cell using input waveform generation considering different circuit topologiesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Feb 7, 2017·2 cites·20 claims
- 2470US8826195B2Layout modification method and systemLEE MENG-XIANG·Filed 2012·Granted Sep 2, 2014·3 cites·20 claims
- 2568US9400866B2Layout modification method and systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jul 26, 2016·1 cites·20 claims
- 2664US2025372589A1System Including an Active Interposer and Method for Manufacturing the SameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2762US8499274B2Computer implemented system and method for leakage calculationCHAO CHIEN-JU·Filed 2012·Granted Jul 30, 2013·2 cites·20 claims
- 2861US2025087589A1Interconnection structure for mult-chip interposer and method of manufacturing sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2958US9122839B2Layout modification method and systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Sep 1, 2015·0 cites·20 claims
- 3055US2025111114A1Method for modeling cross die coupling cap impactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3153US11144485B1Interface for semiconductor device with symmetric bond pattern and method for arranging interface thereofGLOBAL UNICHIP CORP·Filed 2020·Granted Oct 12, 2021·0 cites·26 claims
- 3253US10467364B2Characterizing cell using input waveforms with different tail characteristicsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Nov 5, 2019·0 cites·20 claims
- 3353US10169506B2Circuit design method and systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 1, 2019·0 cites·20 claims
- 3452US9201107B2Cell characterization with Miller capacitanceTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 1, 2015·0 cites·20 claims
- 3551US11687472B2Interface for semiconductor device and interfacing method thereofGLOBAL UNICHIP CORP·Filed 2020·Granted Jun 27, 2023·0 cites·22 claims
- 3651US2025165691A1Method of designing semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3750US11699683B2Semiconductor device in 3D stack with communication interface and managing method thereofGLOBAL UNICHIP CORP·Filed 2020·Granted Jul 11, 2023·0 cites·16 claims
- 3850US2025103786A1Systems and methods for implementing integrated circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3949US11675731B2Data protection system and method thereof for 3D semiconductor deviceGLOBAL UNICHIP CORP·Filed 2020·Granted Jun 13, 2023·0 cites·20 claims
- 4047US9509301B2Voltage control of semiconductor integrated circuitsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Nov 29, 2016·0 cites·21 claims
- 4145US10176284B2Semiconductor circuit design and manufacture methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 8, 2019·0 cites·20 claims
- 4237US10055531B2Layout checking method for advanced double patterning photolithography with multiple spacing criteriaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 21, 2018·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →