Inventor · disambiguated record
Kyong-Mo Bang
Also filed as: BANG KYONG-MO
26 granted patents·7 pending applications·491 citations·filing 2003–2025
96Inventor score
Files withINVENSAS CORP18ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC8TESSERA INC5ADEIA SEMICONDUCTOR TECH LLC1HABA BELGACEM1
Top patents by PatentIndex Score
33 records- 0198US8680684B2Stackable microelectronic package structuresHABA BELGACEM·Filed 2012·Granted Mar 25, 2014·89 cites·36 claims
- 0296US9349707B1Contact arrangements for stackable microelectronic package structures with multiple ranksINVENSAS CORP·Filed 2015·Granted May 24, 2016·29 cites·20 claims
- 0396US7294928B2Components, methods and assemblies for stacked packagesTESSERA INC·Filed 2003·Granted Nov 13, 2007·151 cites·26 claims
- 0494US7246431B2Methods of making microelectronic packages including folded substratesTESSERA INC·Filed 2003·Granted Jul 24, 2007·101 cites·27 claims
- 0592US7053485B2Microelectronic packages with self-aligning featuresTESSERA INC·Filed 2003·Granted May 30, 2006·76 cites·10 claims
- 0691US9484080B1High-bandwidth memory application with controlled impedance loadingINVENSAS CORP·Filed 2015·Granted Nov 1, 2016·8 cites·24 claims
- 0789US12322677B1Fluid channel geometry optimizations to improve cooling efficiencyADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2024·Granted Jun 3, 2025·1 cites·20 claims
- 0889US9425167B2Stackable microelectronic package structuresINVENSAS CORP·Filed 2015·Granted Aug 23, 2016·5 cites·20 claims
- 0985US10008469B2Wafer-level packaging using wire bond wires in place of a redistribution layerINVENSAS CORP·Filed 2016·Granted Jun 26, 2018·4 cites·13 claims
- 1083US8980693B2Stackable microelectronic package structuresINVENSAS CORP·Filed 2014·Granted Mar 17, 2015·4 cites·6 claims
- 1181US9847238B2Fan-out wafer-level packaging using metal foil laminationINVENSAS CORP·Filed 2017·Granted Dec 19, 2017·3 cites·12 claims
- 1279US12341083B2Electronic device cooling structures bonded to semiconductor elementsADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2023·Granted Jun 24, 2025·0 cites·12 claims
- 1378US7935569B2Components, methods and assemblies for stacked packagesTESSERA INC·Filed 2007·Granted May 3, 2011·7 cites·16 claims
- 1477US9928883B2TFD I/O partition for high-speed, high-density applicationsINVENSAS CORP·Filed 2017·Granted Mar 27, 2018·2 cites·10 claims
- 1577US9337170B1Contact arrangements for stackable microelectronic package structuresINVENSAS CORP·Filed 2015·Granted May 10, 2016·3 cites·20 claims
- 1676US9543277B1Wafer level packages with mechanically decoupled fan-in and fan-out areasINVENSAS CORP·Filed 2015·Granted Jan 10, 2017·3 cites·20 claims
- 1774US2025293120A1Electronic device cooling structures bonded to semiconductor elementsADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2025·Application pending·0 cites
- 1872US10566310B2Microelectronic packages having stacked die and wire bond interconnectsINVENSAS CORP·Filed 2016·Granted Feb 18, 2020·2 cites·17 claims
- 1967US12191234B2Integrated cooling assemblies for advanced device packaging and methods of manufacturing the sameADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2023·Granted Jan 7, 2025·0 cites·24 claims
- 2067US9679613B1TFD I/O partition for high-speed, high-density applicationsINVENSAS CORP·Filed 2016·Granted Jun 13, 2017·1 cites·9 claims
- 2164US9646946B2Fan-out wafer-level packaging using metal foil laminationINVENSAS CORP·Filed 2015·Granted May 9, 2017·1 cites·6 claims
- 2264US2025233053A1Integrated cooling assemblies for advanced device packaging and methods of manufacturing the sameADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2024·Application pending·0 cites
- 2363US2025054837A1Electronic device cooling structuresADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2024·Application pending·0 cites
- 2461US2025253206A1Integrated cooling assemblies for advanced device packaging and methods of manufacturing the sameADEIA SEMICONDUCTOR TECH LLC·Filed 2024·Application pending·0 cites
- 2560US9281296B2Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard designINVENSAS CORP·Filed 2014·Granted Mar 8, 2016·1 cites·23 claims
- 2659US10468380B2Stackable microelectronic package structuresINVENSAS CORP·Filed 2018·Granted Nov 5, 2019·0 cites·18 claims
- 2756US2023268300A1Bonded structuresADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2023·Application pending·0 cites
- 2854US9911717B2Stackable microelectronic package structuresINVENSAS CORP·Filed 2015·Granted Mar 6, 2018·0 cites·17 claims
- 2953US2025300040A1Fluid channel geometry optimizations to improve cooling efficiencyADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2025·Application pending·0 cites
- 3051US10026467B2High-bandwidth memory application with controlled impedance loadingINVENSAS CORP·Filed 2016·Granted Jul 17, 2018·0 cites·19 claims
- 3147US9502372B1Wafer-level packaging using wire bond wires in place of a redistribution layerINVENSAS CORP·Filed 2015·Granted Nov 22, 2016·0 cites·20 claims
- 3246US9343398B2BGA ballout partition techniques for simplified layout in motherboard with multiple power supply railINVENSAS CORP·Filed 2014·Granted May 17, 2016·0 cites·22 claims
- 3339US2008156518A1Alignment and cutting of microelectronic substratesTESSERA INC·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →