Inventor · disambiguated record
Lars Liebmann
Also filed as: LIEBMANN LARS · LIEBMANN LARS W · LIEBMANN LARS WOLFGANG
214 granted patents·21 pending applications·5,654 citations·filing 1994–2025
99Inventor score
Top patents by PatentIndex Score
235 records- 0199US10332803B1Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of formingGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 25, 2019·83 cites·20 claims
- 0299US10192819B1Integrated circuit structure incorporating stacked field effect transistorsGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 29, 2019·76 cites·20 claims
- 0399US10090193B1Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 2, 2018·68 cites·20 claims
- 0499US10026824B1Air-gap gate sidewall spacer and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 17, 2018·53 cites·17 claims
- 0599US6993741B2Generating mask patterns for alternating phase-shift mask lithographyIBM·Filed 2003·Granted Jan 31, 2006·313 cites·14 claims
- 0699US6578190B2Process window based optical proximity correction of lithographic imagesIBM·Filed 2001·Granted Jun 10, 2003·289 cites·24 claims
- 0798US10374040B1Method to form low resistance contactGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 6, 2019·48 cites·18 claims
- 0898US9929157B1Tall single-fin fin-type field effect transistor structures and methodsGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 27, 2018·37 cites·13 claims
- 0998US9911619B1Fin cut with alternating two color fin hardmaskGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 6, 2018·24 cites·19 claims
- 1098US9397049B1Gate tie-down enablement with inner spacerIBM·Filed 2015·Granted Jul 19, 2016·25 cites·14 claims
- 1198US6553559B2Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensionsIBM·Filed 2001·Granted Apr 22, 2003·296 cites·38 claims
- 1298US6421820B1Semiconductor device fabrication using a photomask with assist featuresINFINEON TECHNOLOGIES AG·Filed 1999·Granted Jul 16, 2002·293 cites·44 claims
- 1398US6338922B1Optimized alternating phase shifted mask designIBM·Filed 2000·Granted Jan 15, 2002·123 cites·33 claims
- 1498US5740068AFidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correctionIBM·Filed 1996·Granted Apr 14, 1998·300 cites·23 claims
- 1597US12002869B2Gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES US INC·Filed 2022·Granted Jun 4, 2024·4 cites·16 claims
- 1697US11631671B23D complementary metal oxide semiconductor (CMOS) device and method of forming the sameTOKYO ELECTRON LTD·Filed 2020·Granted Apr 18, 2023·5 cites·23 claims
- 1797US11532708B2Stacked three-dimensional field-effect transistorsTOKYO ELECTRON LTD·Filed 2021·Granted Dec 20, 2022·5 cites·12 claims
- 1897US11264274B2Reverse contact and silicide process for three-dimensional logic devicesTOKYO ELECTRON LTD·Filed 2020·Granted Mar 1, 2022·5 cites·20 claims
- 1997US10475692B2Self aligned buried power railGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 12, 2019·14 cites·18 claims
- 2097US10304833B1Method of forming complementary nano-sheet/wire transistor devices with same depth contactsGLOBALFOUNDRIES INC·Filed 2018·Granted May 28, 2019·19 cites·20 claims
- 2197US10236215B1Methods of forming gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 19, 2019·22 cites·19 claims
- 2297US9929048B1Middle of the line (MOL) contacts with two-dimensional self-alignmentGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 27, 2018·22 cites·20 claims
- 2397US9570573B1Self-aligned gate tie-down contacts with selective etch stop linerGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 14, 2017·15 cites·14 claims
- 2497US8647893B1Method for post decomposition density balancing in integrated circuit layouts, related system and program productAGARWAL KANAK B·Filed 2012·Granted Feb 11, 2014·34 cites·20 claims
- 2597US8225255B2Placement and optimization of process dummy cellsOUYANG XU·Filed 2008·Granted Jul 17, 2012·107 cites·5 claims
- 2697US8103983B2Electrically-driven optical proximity correction to compensate for non-optical effectsAGARWAL KANAK B·Filed 2008·Granted Jan 24, 2012·104 cites·20 claims
- 2797US7147976B2Binary OPC for assist feature layout optimizationIBM·Filed 2005·Granted Dec 12, 2006·40 cites·6 claims
- 2897US7115343B2Pliant SRAF for improved performance and manufacturabilityIBM·Filed 2004·Granted Oct 3, 2006·188 cites·17 claims
- 2996US11545497B2CFET SRAM bit cell with three stacked device decksTOKYO ELECTRON LTD·Filed 2020·Granted Jan 3, 2023·3 cites·18 claims
- 3096US10304832B1Integrated circuit structure incorporating stacked field effect transistors and methodGLOBALFOUNDRIES INC·Filed 2017·Granted May 28, 2019·16 cites·15 claims
- 3196US9941162B1Self-aligned middle of the line (MOL) contactsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 10, 2018·13 cites·14 claims
- 3296US9812351B1Interconnection cells having variable width metal lines and fully-self aligned continuity cutsGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 7, 2017·18 cites·20 claims
- 3396US9373582B1Self aligned via in integrated circuitIBM·Filed 2015·Granted Jun 21, 2016·18 cites·8 claims
- 3496US8347240B2Split-layer design for double patterning lithographyIBM·Filed 2010·Granted Jan 1, 2013·26 cites·21 claims
- 3596US7001693B2Binary OPC for assist feature layout optimizationIBM·Filed 2003·Granted Feb 21, 2006·70 cites·13 claims
- 3695US11201152B2Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistorGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 14, 2021·12 cites·5 claims
- 3795US10418484B1Vertical field effect transistors incorporating U-shaped semiconductor bodies and methodsGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 17, 2019·12 cites·20 claims
- 3895US10263122B1Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 16, 2019·14 cites·10 claims
- 3995US9158885B1Reducing color conflicts in triple patterning lithographyIBM·Filed 2014·Granted Oct 13, 2015·52 cites·20 claims
- 4095US8627245B1Density balancing in multiple patterning lithography using integrated circuit layout fillBANERJEE SHAYAK·Filed 2012·Granted Jan 7, 2014·19 cites·17 claims
- 4195US6083275AOptimized phase shift design migrationIBM·Filed 1998·Granted Jul 4, 2000·137 cites·20 claims
- 4295US5636131AGeometric autogeneration of"hard"phase-shift designs for VLSIIBM·Filed 1995·Granted Jun 3, 1997·121 cites·1 claims
- 4395US5553274AVertex minimization in a smart optical proximity correction systemIBM·Filed 1995·Granted Sep 3, 1996·128 cites·3 claims
- 4495US5553273AVertex minimization in a smart optical proximity correction systemIBM·Filed 1995·Granted Sep 3, 1996·128 cites·5 claims
- 4595US5537648AGeometric autogeneration of "hard" phase-shift designs for VLSIIBM·Filed 1994·Granted Jul 16, 1996·143 cites·5 claims
- 4694US9385078B1Self aligned via in integrated circuitIBM·Filed 2016·Granted Jul 5, 2016·11 cites·1 claims
- 4794US7624369B2Closed-loop design for manufacturability processIBM·Filed 2006·Granted Nov 24, 2009·46 cites·21 claims
- 4894US6602728B1Method for generating a proximity model based on proximity rulesIBM·Filed 2001·Granted Aug 5, 2003·73 cites·13 claims
- 4994US5923566APhase shifted design verification routineIBM·Filed 1997·Granted Jul 13, 1999·138 cites·8 claims
- 5094US5807649ALithographic patterning method and mask set therefor with light field trim maskIBM·Filed 1996·Granted Sep 15, 1998·187 cites·20 claims
Showing the top 50 of 235 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →