Inventor · disambiguated record
Lawrence Loh
Also filed as: LOH LAWRENCE · LOH LAWRENCE CHUNKHANG
18 granted patents·1 pending application·254 citations·filing 2001–2016
95Inventor score
Files withCADENCE DESIGN SYSTEMS INC6JASPER DESIGN AUTOMATION INC6JASPER DESIGN AUTOMATION3KRANEN KATHRYN DREWS2INFINEON TECHNOLOGIES CORP1
Top patents by PatentIndex Score
19 records- 0192US8381148B1Formal verification of deadlock propertyJASPER DESIGN AUTOMATION·Filed 2012·Granted Feb 19, 2013·35 cites·35 claims
- 0290US7159198B1System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit modelJASPER DESIGN AUTOMATION·Filed 2003·Granted Jan 2, 2007·63 cites·66 claims
- 0389US10204201B1Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniquesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 12, 2019·12 cites·21 claims
- 0489US9449196B1Security data path verificationJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Sep 20, 2016·15 cites·26 claims
- 0588US8731894B1Indexing behaviors and recipes of a circuit designKRANEN KATHRYN DREWS·Filed 2012·Granted May 20, 2014·10 cites·20 claims
- 0687US8863049B1Constraining traces in formal verificationLUNDGREN LARS·Filed 2010·Granted Oct 14, 2014·16 cites·18 claims
- 0787US7437694B1System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit designJASPER DESIGN AUTOMATION·Filed 2005·Granted Oct 14, 2008·21 cites·19 claims
- 0883US8831925B1Indexing behaviors and recipes of a circuit designKRANEN KATHRYN DREWS·Filed 2010·Granted Sep 9, 2014·6 cites·18 claims
- 0981US9922209B1Security data path verificationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Mar 20, 2018·3 cites·15 claims
- 1081US9633151B1Methods, systems, and computer program product for verifying electronic designs with clock domain crossing pathsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Apr 25, 2017·5 cites·20 claims
- 1181US9104824B1Power aware retention flop list analysis and modificationJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Aug 11, 2015·9 cites·22 claims
- 1280US8954904B1Veryifing low power functionality through RTL transformationJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Feb 10, 2015·8 cites·20 claims
- 1380US7647572B1Managing formal verification complexity of designs with multiple related countersJASPER DESIGN AUTOMATION INC·Filed 2007·Granted Jan 12, 2010·9 cites·24 claims
- 1477US7418678B1Managing formal verification complexity of designs with countersJASPER DESIGN AUTOMATION INC·Filed 2004·Granted Aug 26, 2008·21 cites·29 claims
- 1576US9633153B1Method, system, and computer program product for verifying an electronic design using stall prevention requirements of electronic circuit design models of the electronic designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Apr 25, 2017·7 cites·21 claims
- 1668US7237208B1Managing formal verification complexity of designs with datapathsJASPER DESIGN AUTOMATION INC·Filed 2004·Granted Jun 26, 2007·14 cites·15 claims
- 1754US9934410B1Security data path verificationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Apr 3, 2018·0 cites·15 claims
- 1847US9594861B1Method and system to perform equivalency checksCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 14, 2017·0 cites·29 claims
- 1942US2003061341A1Media cross conversion interfaceINFINEON TECHNOLOGIES CORP·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →