Inventor · disambiguated record
Laung-Terng Wang
Also filed as: WANG LAUNG-TERNG · WANG LAUNG-TERNG L-T
57 granted patents·8 pending applications·1,052 citations·filing 2002–2016
99Inventor score
Files withSYNTEST TECHNOLOGIES INC44WANG LAUNG-TERNG10TOUBA NUR A3STARDFX TECHNOLOGIES INC2SYNTEST TECH INC2
Top patents by PatentIndex Score
65 records- 0197US8522096B2Method and apparatus for testing 3D integrated circuitsWANG LAUNG-TERNG·Filed 2011·Granted Aug 27, 2013·38 cites·36 claims
- 0297US7412637B2Method and apparatus for broadcasting test patterns in a scan based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2006·Granted Aug 12, 2008·62 cites·86 claims
- 0396US7412672B1Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Aug 12, 2008·36 cites·58 claims
- 0496US7058869B2Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Jun 6, 2006·119 cites·34 claims
- 0595US7925947B1X-canceling multiple-input signature register (MISR) for compacting output responses with unknownsSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Apr 12, 2011·36 cites·20 claims
- 0695US7032148B2Mask network design for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Apr 18, 2006·84 cites·76 claims
- 0794US7284175B2Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniquesSYNTEST TECHNOLOGIES INC·Filed 2006·Granted Oct 16, 2007·30 cites·27 claims
- 0894US6954887B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 11, 2005·64 cites·33 claims
- 0993US8775985B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jul 8, 2014·7 cites·2 claims
- 1093US7945833B1Method and apparatus for pipelined scan compressionSYNTEST TECHNOLOGIES INC·Filed 2007·Granted May 17, 2011·29 cites·34 claims
- 1193US7007213B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Feb 28, 2006·52 cites·30 claims
- 1293US6957403B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 18, 2005·69 cites·68 claims
- 1392US7904857B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Mar 8, 2011·20 cites·12 claims
- 1491US7191373B2Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniquesSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Mar 13, 2007·48 cites·19 claims
- 1590US9046572B2Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faultsSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jun 2, 2015·6 cites·32 claims
- 1690US8458544B2Multiple-capture DFT system to reduce peak capture power during self-test or scan testWANG LAUNG-TERNG·Filed 2011·Granted Jun 4, 2013·7 cites·6 claims
- 1790US7231570B2Method and apparatus for multi-level scan compressionSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Jun 12, 2007·21 cites·30 claims
- 1889US8219945B2Computer-aided design system to automate scan synthesis at register-transfer levelWANG LAUNG-TERNG·Filed 2011·Granted Jul 10, 2012·5 cites·4 claims
- 1988US7331032B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Feb 12, 2008·12 cites·11 claims
- 2087US9110139B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2014·Granted Aug 18, 2015·4 cites·21 claims
- 2187US7945830B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2010·Granted May 17, 2011·5 cites·30 claims
- 2287US7512851B2Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Mar 31, 2009·39 cites·46 claims
- 2387US7210082B1Method for performing ATPG and fault simulation in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Apr 24, 2007·16 cites·10 claims
- 2486US8667451B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitWANG LAUNG-TERNG·Filed 2012·Granted Mar 4, 2014·4 cites·12 claims
- 2586US8161441B2Robust scan synthesis for protecting soft errorsWANG LAUNG-TERNG·Filed 2009·Granted Apr 17, 2012·14 cites·16 claims
- 2686US7996741B2Method and apparatus for low-pin-count scan compressionSYNTEST TECHNOLOGIES INC·Filed 2009·Granted Aug 9, 2011·11 cites·46 claims
- 2786US7552373B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Jun 23, 2009·36 cites·44 claims
- 2886US7260756B1Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Aug 21, 2007·11 cites·79 claims
- 2985US8418100B2Robust scan synthesis for protecting soft errorsWANG LAUNG-TERNG·Filed 2012·Granted Apr 9, 2013·6 cites·16 claims
- 3085US7721172B2Method and apparatus for broadcasting test patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2008·Granted May 18, 2010·11 cites·26 claims
- 3184US9121902B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2014·Granted Sep 1, 2015·3 cites·30 claims
- 3284US7124342B2Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Oct 17, 2006·31 cites·102 claims
- 3383US9678156B2Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECH INC·Filed 2016·Granted Jun 13, 2017·3 cites·20 claims
- 3483US7779322B1Compacting test responses using X-driven compactorSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Aug 17, 2010·12 cites·12 claims
- 3583US7590905B2Method and apparatus for pipelined scan compressionSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Sep 15, 2009·13 cites·40 claims
- 3682US7451371B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Nov 11, 2008·9 cites·33 claims
- 3782US7434126B2Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faultsSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Oct 7, 2008·8 cites·7 claims
- 3881US7747920B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Jun 29, 2010·8 cites·24 claims
- 3980US8949299B2Method and apparatus for hybrid ring generator designWANG LAUNG-TERNG·Filed 2011·Granted Feb 3, 2015·6 cites·16 claims
- 4080US8091002B2Multiple-capture DFT system to reduce peak capture power during self-test or scan testWANG LAUNG-TERNG·Filed 2010·Granted Jan 3, 2012·4 cites·6 claims
- 4179US7735049B2Mask network design for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2006·Granted Jun 8, 2010·8 cites·38 claims
- 4278US7444567B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Oct 28, 2008·17 cites·18 claims
- 4377US8402328B2Apparatus and method for protecting soft errorsWANG LAUNG-TERNG·Filed 2009·Granted Mar 19, 2013·8 cites·50 claims
- 4476US9057763B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jun 16, 2015·2 cites·98 claims
- 4576US9026875B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted May 5, 2015·2 cites·55 claims
- 4675US7779323B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Aug 17, 2010·5 cites·21 claims
- 4770US8230282B2Method and apparatus for low-pin-count scan compressionTOUBA NUR A·Filed 2011·Granted Jul 24, 2012·2 cites·10 claims
- 4868US7904773B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Mar 8, 2011·4 cites·34 claims
- 4964US8543950B2Computer-aided design system to automate scan synthesis at register-transfer levelWANG LAUNG-TERNG L-T·Filed 2012·Granted Sep 24, 2013·1 cites·4 claims
- 5059US9316688B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2015·Granted Apr 19, 2016·0 cites·36 claims
Showing the top 50 of 65 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →