Inventor · disambiguated record
Linda Pei Ee Chua
Also filed as: CHUA LINDA PEI EE · CHUA LINDA PEI EI
128 granted patents·25 pending applications·1,259 citations·filing 2007–2025
99Inventor score
Files withDO BYUNG TAI52STATS CHIPPAC LTD44STATS CHIPPAC PTE LTD25PAGAILA REZA A13PAGAILA REZA ARGENTY7
Top patents by PatentIndex Score
153 records- 0199US8097490B1Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor diePAGAILA REZA A·Filed 2010·Granted Jan 17, 2012·155 cites·20 claims
- 0298US9893045B2Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnectSTATS CHIPPAC LTD·Filed 2015·Granted Feb 13, 2018·33 cites·19 claims
- 0398US8283205B2Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor diePAGAILA REZA A·Filed 2012·Granted Oct 9, 2012·47 cites·19 claims
- 0498US7741156B2Semiconductor device and method of forming through vias with reflowed conductive materialSTATS CHIPPAC LTD·Filed 2008·Granted Jun 22, 2010·59 cites·8 claims
- 0598US7553752B2Method of making a wafer level integration packageSTATS CHIPPAC LTD·Filed 2007·Granted Jun 30, 2009·79 cites·17 claims
- 0697US8558392B2Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulantCHUA LINDA PEI EE·Filed 2010·Granted Oct 15, 2013·65 cites·45 claims
- 0797US8492201B2Semiconductor device and method of forming through vias with reflowed conductive materialPAGAILA REZA A·Filed 2010·Granted Jul 23, 2013·29 cites·32 claims
- 0897US8258015B2Integrated circuit package system with penetrable film adhesiveCHOW SENG GUAN·Filed 2008·Granted Sep 4, 2012·55 cites·24 claims
- 0997US7585750B2Semiconductor package having through-hole via on saw streets formed with partial sawSTATS CHIPPAC LTD·Filed 2007·Granted Sep 8, 2009·48 cites·26 claims
- 1096US8378477B2Integrated circuit packaging system with film encapsulation and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2010·Granted Feb 19, 2013·31 cites·20 claims
- 1196US8168458B2Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devicesDO BYUNG TAI·Filed 2008·Granted May 1, 2012·37 cites·25 claims
- 1296US7829998B2Semiconductor wafer having through-hole vias on saw streets with backside redistribution layerSTATS CHIPPAC LTD·Filed 2007·Granted Nov 9, 2010·35 cites·25 claims
- 1396US7659145B2Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the deviceSTATS CHIPPAC LTD·Filed 2008·Granted Feb 9, 2010·38 cites·20 claims
- 1495US8169058B2Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillarsPAGAILA REZA A·Filed 2009·Granted May 1, 2012·29 cites·30 claims
- 1594US8247268B2Semiconductor wafer having through-hole vias on saw streets with backside redistribution layerDO BYUNG TAI·Filed 2010·Granted Aug 21, 2012·16 cites·34 claims
- 1693US9443828B2Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipationSTATS CHIPPAC LTD·Filed 2015·Granted Sep 13, 2016·7 cites·25 claims
- 1793US7843042B2Wafer level integration packageSTATS CHIPPAC LTD·Filed 2009·Granted Nov 30, 2010·22 cites·25 claims
- 1893US7776655B2Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devicesSTATS CHIPPAC LTD·Filed 2008·Granted Aug 17, 2010·20 cites·22 claims
- 1992US9754897B2Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuitsSTATS CHIPPAC LTD·Filed 2015·Granted Sep 5, 2017·8 cites·20 claims
- 2092US9048211B2Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipationSTATS CHIPPAC LTD·Filed 2013·Granted Jun 2, 2015·9 cites·25 claims
- 2192US7989269B2Semiconductor package with penetrable encapsulant joining semiconductor die and method thereofSTATS CHIPPAC LTD·Filed 2008·Granted Aug 2, 2011·20 cites·25 claims
- 2292US7902638B2Semiconductor die with through-hole via on saw streets and through-hole via in active area of dieSTATS CHIPPAC LTD·Filed 2007·Granted Mar 8, 2011·20 cites·15 claims
- 2391US10388612B2Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuitsSTATS CHIPPAC PTE LTD·Filed 2017·Granted Aug 20, 2019·6 cites·21 claims
- 2491US8237252B2Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipationPAGAILA REZA A·Filed 2009·Granted Aug 7, 2012·14 cites·19 claims
- 2591US7977802B2Integrated circuit packaging system with stacked die and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Jul 12, 2011·20 cites·20 claims
- 2690US9679881B2Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill materialSTATS CHIPPAC LTD·Filed 2013·Granted Jun 13, 2017·9 cites·20 claims
- 2790US8592950B2Semiconductor device and method of forming through vias with reflowed conductive materialPAGAILA REZA A·Filed 2010·Granted Nov 26, 2013·8 cites·23 claims
- 2890US8270176B2Exposed interconnect for a package on package systemPAGAILA REZA ARGENTY·Filed 2008·Granted Sep 18, 2012·16 cites·18 claims
- 2990US7968979B2Integrated circuit package system with conformal shielding and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2008·Granted Jun 28, 2011·18 cites·20 claims
- 3090US7923846B2Integrated circuit package-in-package system with wire-in-film encapsulantSTATS CHIPPAC LTD·Filed 2008·Granted Apr 12, 2011·13 cites·9 claims
- 3190US7566966B2Integrated circuit package-on-package system with anti-mold flash featureSTATS CHIPPAC LTD·Filed 2007·Granted Jul 28, 2009·18 cites·20 claims
- 3288US9368423B2Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die packageSTATS CHIPPAC LTD·Filed 2013·Granted Jun 14, 2016·10 cites·34 claims
- 3388US8937379B1Integrated circuit packaging system with trenched leadframe and method of manufacture thereofDO BYUNG TAI·Filed 2013·Granted Jan 20, 2015·10 cites·9 claims
- 3488US7993979B2Leadless package system having external contactsSTATS CHIPPAC LTD·Filed 2007·Granted Aug 9, 2011·13 cites·10 claims
- 3588US7952176B2Integrated circuit packaging system and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2008·Granted May 31, 2011·13 cites·10 claims
- 3688US7709944B2Integrated circuit package system with package integrationSTATS CHIPPAC LTD·Filed 2007·Granted May 4, 2010·16 cites·22 claims
- 3786US9331002B2Semiconductor device and method of forming through vias with reflowed conductive materialSTATS CHIPPAC LTD·Filed 2013·Granted May 3, 2016·5 cites·20 claims
- 3886US8575769B2Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipationPAGAILA REZA A·Filed 2012·Granted Nov 5, 2013·5 cites·24 claims
- 3986US8519518B2Integrated circuit packaging system with lead encapsulation and method of manufacture thereofDO BYUNG TAI·Filed 2010·Granted Aug 27, 2013·8 cites·16 claims
- 4086US8084302B2Semiconductor package having semiconductor die with internal vertical interconnect structure and method thereforDO BYUNG TAI·Filed 2008·Granted Dec 27, 2011·10 cites·36 claims
- 4185US9177901B2Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillarsPAGAILA REZA A·Filed 2012·Granted Nov 3, 2015·6 cites·31 claims
- 4285US8349657B2Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devicesSTATS CHIPPAC LTD·Filed 2012·Granted Jan 8, 2013·5 cites·20 claims
- 4383US9431331B2Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structureSTATS CHIPPAC LTD·Filed 2013·Granted Aug 30, 2016·5 cites·9 claims
- 4482US8823182B2Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulantSTATS CHIPPAC LTD·Filed 2013·Granted Sep 2, 2014·3 cites·25 claims
- 4582US8623708B1Integrated circuit packaging system with grid-array mechanism and method of manufacture thereofDO BYUNG TAI·Filed 2012·Granted Jan 7, 2014·6 cites·5 claims
- 4682US8574960B2Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill materialPAGAILA REZA A·Filed 2010·Granted Nov 5, 2013·5 cites·20 claims
- 4782US7948066B2Integrated circuit package system with lead locking structureSTATS CHIPPAC LTD·Filed 2007·Granted May 24, 2011·7 cites·20 claims
- 4882US7872345B2Integrated circuit package system with rigid locking leadSTATS CHIPPAC LTD·Filed 2008·Granted Jan 18, 2011·10 cites·18 claims
- 4980US8080882B2Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the deviceDO BYUNG TAI·Filed 2009·Granted Dec 20, 2011·7 cites·25 claims
- 5079US9824975B2Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor dieSTATS CHIPPAC LTD·Filed 2015·Granted Nov 21, 2017·2 cites·23 claims
Showing the top 50 of 153 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →