Inventor · disambiguated record
Lisa Mcilwain
Also filed as: MCILWAIN LISA · MCILWAIN LISA R
4 granted patents·49 citations·filing 2002–2021
72Inventor score
Technology areasG06F
Top patents by PatentIndex Score
4 records- 0177US6668362B1Hierarchical verification for equivalence checking of designsSYNOPSYS INC·Filed 2002·Granted Dec 23, 2003·41 cites·20 claims
- 0273US10643012B1Concurrent formal verification of logic synthesisSYNOPSYS INC·Filed 2019·Granted May 5, 2020·3 cites·21 claims
- 0371US8650513B2Reducing x-pessimism in gate-level simulation and verificationSALZ ARTURO·Filed 2011·Granted Feb 11, 2014·5 cites·32 claims
- 0452US11526641B2Formal gated clock conversion for field programmable gate array (FPGA) synthesisSYNOPSYS INC·Filed 2021·Granted Dec 13, 2022·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →