Formal gated clock conversion for field programmable gate array (FPGA) synthesis

Abstract

Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.

What is claimed is: 
     
       1. A method comprising:
 receiving network representation of a circuit design; 
 determining a gated clock function corresponding to a target component of the network representation; 
 constructing an edge function based at least in part on the gated clock function; 
 performing a minimization of the edge function; and 
 in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term. 
 
     
     
       2. The method of  claim 1 , wherein the gated clock function is based on a plurality of inputs corresponding to a support set of the gated clock function. 
     
     
       3. The method of  claim 2 , wherein the edge function returns a logic true value when a transition of an input of the plurality of inputs creates a positive edge on the gated clock function. 
     
     
       4. The method of  claim 2 , wherein the edge function returns a logic true value when a transition of an input of the plurality of inputs creates a negative edge on the gated clock function. 
     
     
       5. The method of  claim 2 , wherein the plurality of inputs comprises one or more of a primary clock signal, an enable signal, a control signal, an output of a flip-flop, and an output of a latch. 
     
     
       6. The method of  claim 1 , further comprising:
 determining whether an edge sensitive input to the gated clock function is remaining; and 
 based on a determination that an edge sensitive input is remaining, constructing the edge function based on the edge sensitive input. 
 
     
     
       7. The method of  claim 1 , wherein the target component is a flip-flop or a latch. 
     
     
       8. A system comprising:
 a memory storing instructions; and 
 a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to: 
 receive network representation of a circuit design; 
 determine a gated clock function corresponding to a target component of the network representation; 
 construct an edge function based at least in part on the gated clock function; 
 perform a minimization of the edge function; and 
 in response to a determination that the minimization of the edge function comprises a first term and a second term, provide a clock enable signal to the target component based on the first term, and provide a clock signal to the target component based on the second term. 
 
     
     
       9. The system of  claim 8 , wherein the gated clock function is based on a plurality of inputs corresponding to a support set of the gated clock function. 
     
     
       10. The system of  claim 9 , wherein the edge function returns a logic true value when a transition of an input of the plurality of inputs creates a positive edge on the gated clock function. 
     
     
       11. The system of  claim 9 , wherein the edge function returns a logic true value when a transition of an input of the plurality of inputs creates a negative edge on the gated clock function. 
     
     
       12. The system of  claim 9 , wherein the plurality of inputs comprises one or more of a primary clock signal, an enable signal, a control signal, an output of a flip-flop, and an output of a latch. 
     
     
       13. The system of  claim 8 , the instructions further cause the processor to:
 determine whether an edge sensitive input to the gated clock function is remaining; and 
 based on a determination that an edge sensitive input is remaining, construct the edge function based on the edge sensitive input. 
 
     
     
       14. The system of  claim 8 , wherein the target component is a flip-flop. 
     
     
       15. A non-transitory computer readable medium comprising stored instructions, which
 when executed by a processor, cause the processor to: 
 receive network representation of a circuit design; 
 determine a gated clock function corresponding to a target component of the network representation; 
 construct an edge function based at least in part on the gated clock function; 
 perform a minimization of the edge function; and 
 in response to a determination that the minimization of the edge function comprises a first term and a second term, provide a clock enable signal to the target component based on the first term, and provide a clock signal to the target component based on the second term. 
 
     
     
       16. The non-transitory computer readable medium of  claim 15 , wherein the gated clock function is based on a plurality of inputs corresponding to a support set of the gated clock function. 
     
     
       17. The non-transitory computer readable medium of  claim 16 , wherein the edge function returns a logic true value when a transition of an input of the plurality of inputs creates a positive edge on the gated clock function. 
     
     
       18. The non-transitory computer readable medium of  claim 16 , wherein the edge function returns a logic true value when a transition of an input of the plurality of inputs creates a negative edge on the gated clock function. 
     
     
       19. The non-transitory computer readable medium of  claim 16 , wherein the plurality of inputs comprises one or more of a primary clock signal, an enable signal, a control signal, an output of a flip-flop, and an output of a latch. 
     
     
       20. The non-transitory computer readable medium of  claim 15 , wherein the stored instructions, when executed, further cause the processor to:
 determine whether an edge sensitive input to the gated clock function is remaining; and 
 based on a determination that an edge sensitive input is remaining, construct the edge function based on the edge sensitive input.