Inventor · disambiguated record
Loic Pallardy
Also filed as: PALLARDY LOIC · PALLARDY LOÏC
16 granted patents·7 pending applications·9 citations·filing 2010–2025
86Inventor score
Files withSTMICROELECTRONICS GRAND OUEST SAS11ST MICROELECTRONICS INT NV4ST MICROELECTRONICS ROUSSET3ST MICROELECTRONICS ALPS SAS2CATROUILLET MICHEL1
Top patents by PatentIndex Score
23 records- 0192US11700174B2Method for managing the operation of a system on chip, and corresponding system on chipST MICROELECTRONICS ALPS SAS·Filed 2020·Granted Jul 11, 2023·4 cites·28 claims
- 0286US12159043B2Dynamic management of a memory firewallSTMICROELECTRONICS GRAND OUEST SAS·Filed 2022·Granted Dec 3, 2024·1 cites·20 claims
- 0383US11876732B2Method for managing the configuration of access to peripherals and their associated resources of a system on chip, and corresponding system on chipST MICROELECTRONICS ROUSSET·Filed 2020·Granted Jan 16, 2024·2 cites·20 claims
- 0472US2025053318A1Dynamic management of a memory firewallSTMICROELECTRONICS GRAND OUEST SAS·Filed 2024·Application pending·0 cites
- 0570US2025371195A1Method for executing a software program by a processing unit comprising a compilation phaseSTMICROELECTRONICS GRAND OUEST SAS·Filed 2025·Application pending·0 cites
- 0664US11962462B2Method for managing the operation of a system on chip, and corresponding system on chipST MICROELECTRONICS ALPS SAS·Filed 2023·Granted Apr 16, 2024·0 cites·19 claims
- 0759US12361173B2Method of managing access rights for software tasks executed by a microcontroller, and corresponding integrated circuitSTMICROELECTRONICS GRAND OUEST SAS·Filed 2022·Granted Jul 15, 2025·0 cites·18 claims
- 0859US12353538B2Method for executing a software program by a processing unit comprising a compilation phaseSTMICROELECTRONICS GRAND OUEST SAS·Filed 2022·Granted Jul 8, 2025·0 cites·19 claims
- 0956US12339762B2Method for monitoring an execution of a program code portion and corresponding system-on-chipSTMICROELECTRONICS GRAND OUEST SAS·Filed 2023·Granted Jun 24, 2025·0 cites·20 claims
- 1055US9601180B2Automatic partial array self-refreshST-ERICSSON SA EN LIQUIDATION·Filed 2013·Granted Mar 21, 2017·2 cites·16 claims
- 1154US11775037B2Method of resetting a master device of a system on chip and corresponding system on chipST MICROELECTRONICS GRENOBLE 2·Filed 2021·Granted Oct 3, 2023·0 cites·22 claims
- 1254US2024406163A1Method for managing the life cycle of a system-on-chip, and corresponding system-on-chipST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1354US2024320359A1System-on-chip including resource isolation framework and countermeasure circuit, and corresponding methodST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1452US2024176689A1Method for managing the isolation of resources of a system-on-chip, and corresponding system-on-chipSTMICROELECTRONICS GRAND OUEST SAS·Filed 2023·Application pending·0 cites
- 1551US12455692B2Management of a memory firewall in a system on chipSTMICROELECTRONICS GRAND OUEST SAS·Filed 2022·Granted Oct 28, 2025·0 cites·20 claims
- 1650US12373374B2Method for managing the operation of a system on chip, and corresponding system on chipST MICROELECTRONICS ROUSSET·Filed 2022·Granted Jul 29, 2025·0 cites·20 claims
- 1750US2024370382A1System-on-chip having a memory controller and corresponding memory control methodST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1849US12292777B2Management of a low-power modeSTMICROELECTRONICS GRAND OUEST SAS·Filed 2021·Granted May 6, 2025·0 cites·20 claims
- 1948US10025726B2Method in a memory management unit for managing address translations in two stagesST MICROELECTRONICS INT NV·Filed 2014·Granted Jul 17, 2018·0 cites·20 claims
- 2048US2023161486A1Method for managing a memory in a system-on-a-chipSTMICROELECTRONICS GRAND OUEST SAS·Filed 2022·Application pending·0 cites
- 2147US11829188B2Method for managing the debugging of a system on chip forming for example a microcontroller, and corresponding system on chipST MICROELECTRONICS ROUSSET·Filed 2020·Granted Nov 28, 2023·0 cites·20 claims
- 2245US11614949B2Method and device for managing operation of a computing unit capable of operating with instructions of different sizesSTMICROELECTRONICS GRAND OUEST SAS·Filed 2020·Granted Mar 28, 2023·0 cites·22 claims
- 2325US9390029B2Dynamic management of random access memoryCATROUILLET MICHEL·Filed 2010·Granted Jul 12, 2016·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →