Inventor · disambiguated record
Luona Goh
Also filed as: GOH LUONA
5 granted patents·3 pending applications·49 citations·filing 2001–2011
78Inventor score
Top patents by PatentIndex Score
8 records- 0174US7224060B2Integrated circuit with protective moatCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted May 29, 2007·25 cites·24 claims
- 0273US6797605B2Method to improve adhesion of dielectric films in damascene interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 28, 2004·17 cites·19 claims
- 0359US8013372B2Integrated circuit including a stressed dielectric layer with stable stressGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Sep 6, 2011·2 cites·9 claims
- 0453US8999863B2Stress liner for stress engineeringLEE JAE GON·Filed 2008·Granted Apr 7, 2015·1 cites·24 claims
- 0553US7078333B2Method to improve adhesion of dielectric films in damascene interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Jul 18, 2006·4 cites·11 claims
- 0641US2009315121A1Stable stress dielectric layerCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 0741US2009289284A1High shrinkage stress silicon nitride (SiN) layer for NFET improvementCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 0837US2011316085A1Integrated circuit including a stressed dielectric layer with stable stressLIU HUANG·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →