Integrated circuit including a stressed dielectric layer with stable stress

Abstract

An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O 3 TEOS oxide having a stress retaining dopant. The O 3 TEOS oxide induces a stress in a channel region of the transistor.

1 . An integrated circuit (IC) comprising:
 a substrate having active and isolation regions; and   a transistor disposed on the substrate in the active region, the transistor having a channel region,   wherein the isolation region comprises O 3  TEOS oxide having a stress retaining dopant, the O 3  TEOS oxide induces a first stress in the channel region of the transistor.   
     
     
         2 . The IC of  claim 1  wherein the stress retaining dopant comprises nitrogen. 
     
     
         3 . The IC of  claim 2  wherein the nitrogen comprises a concentration of about 1E6-1E15 c/s. 
     
     
         4 . The IC of  claim 1  wherein the transistor comprises n-type transistor and the first stress is tensile stress. 
     
     
         5 . The IC of  claim 1  wherein the transistor comprises p-type transistor and the first stress is tensile stress. 
     
     
         6 . An integrated circuit (IC) comprising:
 a substrate having active and isolation regions;   a transistor disposed on the substrate in the active region, the transistor having a channel region; and   a dielectric layer disposed on the substrate and the transistor,   wherein at least one of the isolation region or the dielectric layer comprises O 3  TEOS oxide having a stress retaining dopant, the O 3  TEOS oxide induces a first stress in the channel region of the transistor.   
     
     
         7 . The IC of  claim 6  wherein the dielectric layer comprises a pre-metal dielectric (PMD) layer. 
     
     
         8 . The IC of  claim 7  wherein the stress retaining dopant comprises nitrogen. 
     
     
         9 . The IC of  claim 8  wherein the nitrogen comprises a concentration of about 1E6-1E15 c/s. 
     
     
         10 . The IC of  claim 6  wherein the transistor comprises n-type transistor and the first stress is tensile stress. 
     
     
         11 . The IC of  claim 6  wherein the isolation region comprises shallow trench isolation region.