Inventor · disambiguated record
Wei Lu
Also filed as: LU WEI · LU WEI-SHIN
26 granted patents·4 pending applications·151 citations·filing 1995–2016
95Inventor score
Files withGLOBALFOUNDRIES SG PTE LTD17CHARTERED SEMICONDUCTOR MFG10LIM SIN LENG1LIU HUANG1NAT SCIENCE COUNSIL1
Top patents by PatentIndex Score
30 records- 0195US7271110B2High density plasma and bias RF power process to make stable FSG with less free F and SiN with less H to enhance the FSG/SiN integration reliabilityCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Sep 18, 2007·32 cites·18 claims
- 0289US9511474B2CMP head structure with retaining ringGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Dec 6, 2016·3 cites·20 claims
- 0387US7566656B2Method and apparatus for providing void structuresCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Jul 28, 2009·17 cites·31 claims
- 0485US7790617B2Formation of metal silicide layer over copper interconnect for reliability enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Sep 7, 2010·11 cites·29 claims
- 0584US9520371B2Planar passivation for padsGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Dec 13, 2016·6 cites·20 claims
- 0683US9287197B2Through silicon viasGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Mar 15, 2016·6 cites·20 claims
- 0781US8264088B2Planarized passivation layer for semiconductor devicesLIM SIN LENG·Filed 2011·Granted Sep 11, 2012·5 cites·13 claims
- 0881US7745320B2Method for reducing silicide defects in integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Jun 29, 2010·7 cites·21 claims
- 0980US9242341B2CMP head structureGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Jan 26, 2016·3 cites·20 claims
- 1080US7892900B2Integrated circuit system employing sacrificial spacersGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Feb 22, 2011·9 cites·20 claims
- 1178US9443761B2Methods for fabricating integrated circuits having device contactsGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Sep 13, 2016·4 cites·9 claims
- 1275US9437547B2Through silicon viasGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Sep 6, 2016·2 cites·20 claims
- 1373US8354347B2Method of forming high-k dielectric stop layer for contact hole openingGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Jan 15, 2013·6 cites·29 claims
- 1472US9620418B2Methods for fabricating integrated circuits with improved active regionsGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Apr 11, 2017·3 cites·17 claims
- 1570US7855143B2Interconnect capping layer and method of fabricationCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Dec 21, 2010·3 cites·19 claims
- 1669US5683946AMethod for manufacturing fluorinated gate oxide layerNAT SCIENCE COUNSIL·Filed 1995·Granted Nov 4, 1997·29 cites·20 claims
- 1767US9242338B2CMP head structureGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Jan 26, 2016·1 cites·20 claims
- 1862US9511470B2CMP head structure with retaining ringGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Dec 6, 2016·0 cites·20 claims
- 1960US9349654B2Isolation for embedded devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted May 24, 2016·1 cites·21 claims
- 2059US8013372B2Integrated circuit including a stressed dielectric layer with stable stressGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Sep 6, 2011·2 cites·9 claims
- 2157US7332422B2Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatmentCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Feb 19, 2008·1 cites·12 claims
- 2252US9153473B2Wafer processingGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Oct 6, 2015·0 cites·20 claims
- 2350US9627219B2CMP wafer edge control of dielectricGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Apr 18, 2017·0 cites·21 claims
- 2448US9202746B2Integrated circuits with improved gap fill dielectric and methods for fabricating sameGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Dec 1, 2015·0 cites·20 claims
- 2548US7960283B2Method for reducing silicide defects in integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 2010·Granted Jun 14, 2011·0 cites·20 claims
- 2642US2010109155A1Reliable interconnect integrationCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2741US2009315121A1Stable stress dielectric layerCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2841US2009289284A1High shrinkage stress silicon nitride (SiN) layer for NFET improvementCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2937US2011316085A1Integrated circuit including a stressed dielectric layer with stable stressLIU HUANG·Filed 2011·Application pending·0 cites
- 3036US7998831B2Planarized passivation layer for semiconductor devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Aug 16, 2011·0 cites·35 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →