Inventor · disambiguated record
Luke Yen
Also filed as: YEN LUKE · YEN LUKE B R
14 granted patents·8 pending applications·69 citations·filing 1998–2025
88Inventor score
Files withADVANCED MICRO DEVICES INC7QUALCOMM INC6TENSTORRENT AL ULC2TENSTORRENT USA INC2CHUNG JAEWOONG1
Top patents by PatentIndex Score
22 records- 0192US8239633B2Non-broadcast signature-based transactional memoryWOOD DAVID A·Filed 2008·Granted Aug 7, 2012·45 cites·22 claims
- 0286US8543775B2Preventing unintended loss of transactional data in hardware transactional memory systemsADVANCED MICRO DEVICES INC·Filed 2012·Granted Sep 24, 2013·8 cites·31 claims
- 0379US10956163B2Processor support for hardware transactional memoryADVANCED MICRO DEVICES INC·Filed 2017·Granted Mar 23, 2021·2 cites·8 claims
- 0475US9710276B2Execution of instruction loops using an instruction bufferADVANCED MICRO DEVICES INC·Filed 2012·Granted Jul 18, 2017·5 cites·22 claims
- 0575US8352688B2Preventing unintended loss of transactional data in hardware transactional memory systemsADVANCED MICRO DEVICES INC·Filed 2010·Granted Jan 8, 2013·3 cites·20 claims
- 0670US2025138624A1Automotive Computing Architecture with Phased Wake Sequence and Power ControlTENSTORRENT AL ULC·Filed 2024·Application pending·0 cites
- 0770US2025141729A1Scale Out Compatibility Chiplets for Automotive Computing ArchitectureTENSTORRENT AL ULC·Filed 2024·Application pending·0 cites
- 0863US9880848B2Processor support for hardware transactional memoryCHUNG JAEWOONG·Filed 2010·Granted Jan 30, 2018·1 cites·18 claims
- 0954US9152509B2Transactional memory conflict managementDIESTELHORST STEPHAN·Filed 2011·Granted Oct 6, 2015·1 cites·20 claims
- 1052US2025335363A1Transaction and Request Buffers for Cache Miss HandlingTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 1149US11669333B2Method, apparatus, and system for reducing live readiness calculations in reservation stationsQUALCOMM INC·Filed 2018·Granted Jun 6, 2023·0 cites·15 claims
- 1249US10877895B2Method, apparatus, and system for prefetching exclusive cache coherence state for store instructionsQUALCOMM INC·Filed 2018·Granted Dec 29, 2020·0 cites·23 claims
- 1349US9459877B2Nested speculative regions for a synchronization facilityADVANCED MICRO DEVICES INC·Filed 2012·Granted Oct 4, 2016·0 cites·13 claims
- 1449US9367310B2Stack access tracking using dedicated tableADVANCED MICRO DEVICES INC·Filed 2013·Granted Jun 14, 2016·0 cites·20 claims
- 1549US9292292B2Stack access trackingADVANCED MICRO DEVICES INC·Filed 2013·Granted Mar 22, 2016·0 cites·15 claims
- 1647US10860328B2Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architectureQUALCOMM INC·Filed 2018·Granted Dec 8, 2020·0 cites·42 claims
- 1747US2025328456A1Window-Based Memory Dependency PredictorTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 1843US2019155608A1Fast pipeline restart in processor with decoupled fetcherQUALCOMM INC·Filed 2018·Application pending·0 cites
- 1939US2013159673A1Providing capacity guarantees for hardware transactional memory systems using fencesPOHLACK MARTIN T·Filed 2011·Application pending·0 cites
- 2037US2017046158A1Determining prefetch instructions based on instruction encodingQUALCOMM INC·Filed 2015·Application pending·0 cites
- 2135US2017046167A1Predicting memory instruction punts in a computer processor using a punt avoidance table (pat)QUALCOMM INC·Filed 2015·Application pending·0 cites
- 2223US6321215B1Examining method of learning performance with computerINVENTEC CORP·Filed 1998·Granted Nov 20, 2001·4 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →