Inventor · disambiguated record
Mark A. Bachman
Also filed as: BACHMAN MARK · BACHMAN MARK A · BACHMAN MARK ADAM
19 granted patents·6 pending applications·191 citations·filing 2003–2015
94Inventor score
Top patents by PatentIndex Score
25 records- 0196US8492911B2Stacked interconnect heat sinkBACHMAN MARK A·Filed 2010·Granted Jul 23, 2013·34 cites·7 claims
- 0295US8987137B2Method of fabrication of through-substrate viasBACHMAN MARK A·Filed 2010·Granted Mar 24, 2015·25 cites·18 claims
- 0392US7952206B2Solder bump structure for flip chip semiconductor devices and method of manufacture thereforeAGERE SYSTEMS INC·Filed 2006·Granted May 31, 2011·20 cites·10 claims
- 0491US8742535B2Integration of shallow trench isolation and through-substrate vias into integrated circuit designsBACHMAN MARK A·Filed 2010·Granted Jun 3, 2014·13 cites·9 claims
- 0590US8378485B2Solder interconnect by addition of copperLSI CORP·Filed 2009·Granted Feb 19, 2013·16 cites·23 claims
- 0682US8507317B2Solder bump structure for flip chip semiconductor devices and method of manufacturing thereforeBACHMAN MARK A·Filed 2011·Granted Aug 13, 2013·5 cites·7 claims
- 0782US8319343B2Routing under bond pad for the replacement of an interconnect layerARCHER III VANCE D·Filed 2006·Granted Nov 27, 2012·13 cites·10 claims
- 0879US7777333B2Structure and method for fabricating flip chip devicesAGERE SYSTEMS INC·Filed 2006·Granted Aug 17, 2010·9 cites·17 claims
- 0976US7328830B2Structure and method for bonding to copper interconnect structuresAGERE SYSTEMS INC·Filed 2003·Granted Feb 12, 2008·22 cites·16 claims
- 1075US9613847B2Integration of shallow trench isolation and through-substrate vias into integrated circuit designsLSI CORP·Filed 2014·Granted Apr 4, 2017·3 cites·15 claims
- 1172US8580621B2Solder interconnect by addition of copperLSI CORP·Filed 2013·Granted Nov 12, 2013·2 cites·10 claims
- 1267US8779587B2PB-free solder bumps with improved mechanical propertiesBACHMAN MARK·Filed 2008·Granted Jul 15, 2014·3 cites·6 claims
- 1367US6960836B2Reinforced bond padAGERE SYSTEMS INC·Filed 2003·Granted Nov 1, 2005·13 cites·6 claims
- 1465US7724359B2Method of making electronic entitiesAGERE SYSTEMS INC·Filed 2008·Granted May 25, 2010·2 cites·14 claims
- 1562US7479695B2Low thermal resistance assembly for flip chip applicationsAGERE SYSTEMS INC·Filed 2006·Granted Jan 20, 2009·3 cites·20 claims
- 1660US7671436B2Electronic packagesAGERE SYSTEMS INC·Filed 2008·Granted Mar 2, 2010·2 cites·21 claims
- 1756US9054064B2Stacked interconnect heat sinkLSI CORP·Filed 2013·Granted Jun 9, 2015·0 cites·7 claims
- 1855US7221173B2Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping processAGERE SYSTEMS INC·Filed 2004·Granted May 22, 2007·6 cites·10 claims
- 1954US9443821B2Pb-free solder bumps with improved mechanical propertiesBACHMAN MARK·Filed 2014·Granted Sep 13, 2016·0 cites·20 claims
- 2052US2014015127A1Contact support pillar structure for flip chip semiconductor devices and method of manufacture thereforeAGERE SYSTEMS LLC·Filed 2013·Application pending·0 cites
- 2148US2015214130A1Stacked interconnect heat sinkAVAGO TECHNOLOGIES GENERAL IP·Filed 2015·Application pending·0 cites
- 2248US2011006389A1Suppressing fractures in diced integrated circuitsLSI CORP·Filed 2009·Application pending·0 cites
- 2348US2013056868A1Routing under bond pad for the replacement of an interconnect layerAGERE SYSTEMS LLC·Filed 2012·Application pending·0 cites
- 2446US2010319967A1Inhibition of copper dissolution for lead-free solderingAGERE SYSTEMS INC·Filed 2007·Application pending·0 cites
- 2545US2010052174A1Copper pad for copper wire bondingAGERE SYSTEMS INC·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →