Contact support pillar structure for flip chip semiconductor devices and method of manufacture therefore

Abstract

In one aspect, there is provided a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and has a contact support pillar opening formed therein. Contact support pillars that comprise a conductive metal and have a metal extension are located within the opening of the passivation layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 an interconnect layer located over a semiconductor substrate;   a passivation layer located over the interconnect layer and having an opening formed therein;   contact support pillars located within the opening, the contact support pillars comprising a metal and having a metal extension thereon.   
     
     
         2 . The semiconductor device recited in  claim 1 , wherein the contact support pillars and the metal extension have a different metallic composition. 
     
     
         3 . The semiconductor device recited in  claim 2 , wherein the metal is gold and the extensions are comprised of a gold alloy. 
     
     
         4 . The semiconductor device recited in  claim 1 , wherein the semiconductor device comprises opposing integrated circuit (IC) flip chips, each comprising the contact support pillars and the extensions, the extensions of the IC flip chips contacting each other to provide electrical connection between the IC flip chips. 
     
     
         5 . The semiconductor device recited in  claim 3 , wherein the contact support pillars include a barrier layer and a gold seed layer located over the barrier layer. 
     
     
         6 . The semiconductor device recited in  claim 3 , wherein the gold alloy extension comprises gold/tin, gold/germanium, or gold/silicon. 
     
     
         7 . A semiconductor device, comprising:
 an interconnect layer located over a semiconductor substrate;   a passivation layer located over the interconnect layer and having openings formed therein;   contact support pillars located within the openings, the contact support pillars comprising a metal and having a metal extension thereon.   
     
     
         8 . The semiconductor device recited in  claim 7 , wherein the semiconductor device comprises opposing integrated circuit (IC) flip chips, each comprising the contact support pillars and the extensions, the extensions of the IC flip chips contacting each other to provide electrical connection between the IC flip chips. 
     
     
         9 . The semiconductor device recited in  claim 7 , wherein the metal is gold and the extensions are comprised of a gold alloy. 
     
     
         10 . The semiconductor device recited in  claim 9 , wherein the gold alloy extension comprises gold/tin, gold/germanium, or gold/silicon. 
     
     
         11 . The semiconductor device recited in  claim 9 , wherein the contact support pillars include a barrier layer and a gold seed layer located over the barrier layer. 
     
     
         12 . The semiconductor device recited in  claim 7 , wherein portions of the passivation layer are located between the contact support pillars. 
     
     
         13 . A method of fabricating a semiconductor device, comprising:
 providing a semiconductor substrate having an interconnect located thereover;   forming openings in the passivation layer located over the interconnect;   forming contact support pillars in the openings of the passivation layer from a conductive metal;   depositing a photoresist over the passivation layer and the contact support pillars;   forming extension openings in the photoresist such that the extension openings substantially align with the contact support pillars;   depositing a conductive metal alloy in the extension openings to form contact extensions on the contact support pillars; and   removing the photoresist such that the contact extensions extend above the passivation layer.   
     
     
         14 . The method recited in  claim 13 , wherein the conductive metal comprises gold and the conductive metal alloy is a gold alloy. 
     
     
         15 . The method recited in  claim 13 , wherein the semiconductor device comprises opposing integrated circuit (IC) flip chips, comprising the gold support pillars and the gold alloy extensions and the method comprises:
 placing the gold alloy extensions of each of the IC flip chips in substantial contact with each other and reflowing the gold alloy extensions to provide electrical connection between the IC flip chips.   
     
     
         16 . The method recited in  claim 13  wherein portions of the passivation layer are located between the contact support pillars. 
     
     
         17 . A method of fabricating a semiconductor device, comprising:
 providing a semiconductor substrate having an interconnect located thereover;   creating an opening in a passivation layer located over the interconnect;
 depositing a sacrificial layer over the passivation layer and within the opening; 
   forming openings in the sacrificial layer located within the opening;   depositing a conductive metal within the openings to create the contact support pillars;   depositing a photoresist over the sacrificial layer and the contact support pillars;   forming extension openings in the photoresist such that the extension openings substantially align with respective contact support pillars;   depositing a conductive metal alloy in the extension openings to form support pillar extensions;   removing the photoresist; and   removing the sacrificial layer.   
     
     
         18 . The method recited in  claim 17 , wherein the conductive metal is gold and the conductive metal alloy comprises a gold alloy. 
     
     
         19 . The method recited in  claim 17 , wherein the semiconductor device comprises opposing integrated circuit (IC) flip chips, each comprising the contact support pillars and the metal extensions and the method further comprises:
 placing the extensions of each of the IC flip chips in substantial contact with each other and reflowing the extensions to provide electrical connection between the IC flip chips.   
     
     
         20 . The method recited in  claim 17 , wherein, the conductive metal and the conductive metal alloy have a different metallic composition. 
     
     
         21 . A semiconductor device, comprising:
 an interconnect layer located over a semiconductor substrate;   a passivation layer located over the interconnect layer and having an opening formed therein;   a contact support pillar located within the opening, the contact support pillar comprising a metal and having a metal extension thereon.   
     
     
         22 . The semiconductor device recited in  claim 21 , wherein the contact support pillar and the metal extension have a different metallic composition. 
     
     
         23 . The semiconductor device recited in  claim 22 , wherein the metal is gold and the extension is comprised of a gold alloy. 
     
     
         24 . The semiconductor device recited in  claim 21 , wherein the semiconductor device comprises opposing first and second integrated circuit (IC) flip chips, each of the first and second flip chips comprise the contact support pillar and the extension, the extension of the contact support pillar of the first IC flip chip contacting the extension of the contact support pillar of the second IC flip chip to provide electrical connection between the first and second IC flip chips. 
     
     
         25 . The semiconductor device recited in  claim 21 , wherein the semiconductor device comprises opposing first and second integrated circuit (IC) flip chips, each of the first and second flip chips comprising the contact support pillars and the extensions, the extensions of the contact support pillars of the first IC flip chip contacting corresponding ones of the extensions of the contact support pillars of the second IC flip chip to provide electrical connection between the first and second IC flip chips.