Routing under bond pad for the replacement of an interconnect layer

Abstract

The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

1 . A semiconductor device, comprising:
 active devices located over a semiconductor substrate;   an outermost interconnect layer segmented into at least first and second runner portions formed over the active devices; and   a segmented bond pad layer positioned over the outermost interconnect layer, the bond pad layer comprising a bond pad portion and an interconnect runner portion;   a passivation layer located between the outermost interconnect layer and the bond pad layer, the passivation layer having openings extending therethrough and to the outermost interconnect layer, wherein the bond pad and interconnect runner portions extend into and through at least one of the openings and contact the first portion and the second portion, respectively; and   an under bump metallization (UBM) layer located over the bond pad portion.   
     
     
         2 . The device recited in  claim 1 , wherein a solder bump is located on the UBM layer. 
     
     
         3 . The device recited in  claim 1 , wherein the passivation layer is a wafer passivation layer and the device further comprises a final passivation layer located over the at least one interconnect runner portion and wherein a portion of the UBM layer is located over the final passivation layer. 
     
     
         4 . The device recited in  claim 1 , wherein the bond pad layer comprises aluminum or alloys thereof and the outermost interconnect layer comprises copper or alloys thereof. 
     
     
         5 . The device recited in  claim 1 , wherein the first portion is divided into a first plurality of runners and the second portion is divided into a second plurality of runners and the bond pad portion is electrically connected to each of the first plurality by a portion of the bond pad that extends through at least one of the openings and the interconnect runner portion is electrically connected to each of the second plurality by a portion of the interconnect portion that extends through at least one of the other openings. 
     
     
         6 . An integrated circuit, comprising:
 transistors located over a semiconductor substrate;   dielectric layers located over the transistors;   interconnect layers comprising copper formed over the transistors and within the dielectric layers; and   an outermost metallization layer positioned over the interconnect layers, the outermost metallization layer comprising aluminum and divided into a plurality of bond pads and a plurality of interconnect runners each electrically connected to an outermost interconnect layer by a portion of each of the bond pads and interconnect runners extending through openings in an underlying layer and to the outermost interconnect layer.   
     
     
         7 . The device recited in  claim 6 , wherein an under bump metallization (UBM) layer is located over the at least one bond pad. 
     
     
         8 . The device recited in  claim 7 , wherein a solder bump is located on the UBM layer. 
     
     
         9 . The device recited in  claim 6 , wherein the under lying layer is a passivation layer located between the outermost interconnect layer and the outermost metallization layer, the passivation layer having openings extending therethrough and contacting the outermost interconnect layer and wherein the outermost metallization layer extends into and through the openings. 
     
     
         10 . The device recited in  claim 9 , further comprising an under bump metallization (UBM) layer located over each of the bond pads. 
     
     
         11 . The device recited in  claim 10 , wherein the passivation layer is a wafer passivation layer and the device further comprises a final passivation layer located over the interconnect runners and a portion of each of the bond pads. 
     
     
         12 . The device recited in  claim 6 , wherein the outermost metallization layer comprises an aluminum alloy. 
     
     
         13 . The device recited in  claim 6 , wherein the outermost interconnect layer is segmented into a plurality of outermost interconnect runners and wherein each of the bond pads is electrically connected to a different one of the outermost interconnect runners by a portion of the bond pad extending into and through at least one of the openings and each of the interconnect runners of the outermost metallization layer is electrically connected to a different one of the outermost interconnect layers by a portion of the interconnect runner extending into and through at least one of the openings. 
     
     
         14 . A method of manufacturing a semiconductor device, comprising:
 forming a copper interconnect layer over a semiconductor substrate;   forming a passivation layer over the copper interconnect layer; and   forming an aluminum layer including at least one bond pad and at least one interconnect runner over the passivation layer, wherein the at least one bond pad and the at least one interconnect runner contacts the copper interconnect layer by a portion of the at least one bond pad extending through at least one opening in the passivation and by a portion of the at least one interconnect runner extending through another of the at least one opening in the passivation layer.   
     
     
         15 . The method recited in  claim 14 , wherein forming the copper interconnect layer includes segmenting the copper interconnect layer. 
     
     
         16 . The method recited in  claim 15 , further comprising forming an under bump metallization (UBM) layer over the at least one bond pad and wherein a solder bump is located on the UBM layer. 
     
     
         17 . The method recited in  claim 16 , wherein the solder bump comprises lead or its alloys or is lead-free. 
     
     
         18 . The method recited in  claim 16 , wherein the copper interconnect layer is an outermost metallization interconnect layer. 
     
     
         19 . The method recited in  claim 16 , wherein the passivation layer is a wafer passivation layer and the device further comprises a final passivation layer located over the at least one interconnect runner and wherein a portion of the UBM layer is located over the final passivation layer. 
     
     
         20 . The method recited in  claim 14 , wherein the aluminum layer comprises an aluminum alloy. 
     
     
         21 . The method recited in  claim 14 , wherein the copper interconnect layer comprises a copper alloy. 
     
     
         22 . A semiconductor device, comprising:
 active devices located over a semiconductor substrate;   interconnect layers comprising copper formed over the active devices; and   an outermost metallization layer positioned over the interconnect layers, wherein the outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer by a portion of the at least one bond pad extending through at least one opening in an underlying layer and by a portion of the at least one interconnect layer extending through at least one other opening in the underlying layer.