Inventor · disambiguated record
Martin Gerhardt
Also filed as: GERHARDT MARTIN
22 granted patents·4 pending applications·107 citations·filing 2005–2022
94Inventor score
Files withGLOBALFOUNDRIES INC12ADVANCED MICRO DEVICES INC5GERHARDT MARTIN5BSH HAUSGERAETE GMBH1FLACHOWSKY STEFAN1
Top patents by PatentIndex Score
26 records- 0190US7494906B2Technique for transferring strain into a semiconductor regionADVANCED MICRO DEVICES INC·Filed 2005·Granted Feb 24, 2009·22 cites·35 claims
- 0288US9922986B2Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereofGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 20, 2018·5 cites·20 claims
- 0388US7348233B1Methods for fabricating a CMOS device including silicide contactsADVANCED MICRO DEVICES INC·Filed 2005·Granted Mar 25, 2008·17 cites·16 claims
- 0487US7462524B1Methods for fabricating a stressed MOS deviceADVANCED MICRO DEVICES INC·Filed 2005·Granted Dec 9, 2008·15 cites·7 claims
- 0586US8349694B2Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloyGLOBALFOUNDRIES INC·Filed 2010·Granted Jan 8, 2013·9 cites·18 claims
- 0685US7964970B2Technique for enhancing transistor performance by transistor specific contact designGLOBALFOUNDRIES INC·Filed 2007·Granted Jun 21, 2011·11 cites·17 claims
- 0779US9136177B2Methods of forming transistor devices with high-k insulation layers and the resulting devicesGERHARDT MARTIN·Filed 2012·Granted Sep 15, 2015·5 cites·19 claims
- 0879US7871877B2Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel regionGLOBALFOUNDRIES INC·Filed 2008·Granted Jan 18, 2011·6 cites·18 claims
- 0972US8541885B2Technique for enhancing transistor performance by transistor specific contact designGERHARDT MARTIN·Filed 2011·Granted Sep 24, 2013·3 cites·8 claims
- 1071US9461145B2OPC enlarged dummy electrode to eliminate ski slope at eSiGeGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 4, 2016·2 cites·10 claims
- 1168US9117929B2Method for forming a strained transistor by stress memorization based on a stressed implantation maskWIRBELEIT FRANK·Filed 2011·Granted Aug 25, 2015·2 cites·18 claims
- 1268US7659170B2Method of increasing transistor drive current by recessing an isolation trenchGLOBALFOUNDRIES INC·Filed 2007·Granted Feb 9, 2010·5 cites·13 claims
- 1366US10580863B2Transistor element with reduced lateral electrical fieldGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 3, 2020·1 cites·2 claims
- 1466US9425194B2Transistor devices with high-k insulation layersGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 23, 2016·1 cites·19 claims
- 1561US7994059B2Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Aug 9, 2011·2 cites·9 claims
- 1659US7964458B2Method for forming a strained transistor by stress memorization based on a stressed implantation maskGLOBALFOUNDRIES INC·Filed 2007·Granted Jun 21, 2011·1 cites·14 claims
- 1755US10529728B2Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cellGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 7, 2020·0 cites·20 claims
- 1848US12088101B2Circuit arrangement for controlling a plurality of electrical loadsBSH HAUSGERAETE GMBH·Filed 2022·Granted Sep 10, 2024·0 cites·18 claims
- 1947US2010047985A1Method for fabricating a semiconductor device with self-aligned stressor and extension regionsADVANCED MICRO DEVICES INC·Filed 2008·Application pending·0 cites
- 2046US10256134B2Heat dissipative element for polysilicon resistor bankGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 9, 2019·0 cites·18 claims
- 2146US9219013B2Technique for manufacturing semiconductor devices comprising transistors with different threshold voltagesGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 22, 2015·0 cites·16 claims
- 2241US8101512B2Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topographyGERHARDT MARTIN·Filed 2007·Granted Jan 24, 2012·0 cites·20 claims
- 2339US8614134B2Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantationGERHARDT MARTIN·Filed 2011·Granted Dec 24, 2013·0 cites·20 claims
- 2438US2007232033A1Method for forming ultra-shallow high quality junctions by a combination of solid phase epitaxy and laser annealingWIECZOREK KARSTEN·Filed 2006·Application pending·0 cites
- 2538US2014070321A1Integrated circuits having boron-doped silicon germanium channels and methods for fabricating the sameGERHARDT MARTIN·Filed 2012·Application pending·0 cites
- 2637US2013095627A1Methods of Forming Source/Drain Regions on Transistor DevicesFLACHOWSKY STEFAN·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →