Inventor · disambiguated record
Ma Phoo Pwint Hlaing
Also filed as: HLAING MA PHOO PWINT
6 granted patents·51 citations·filing 2010–2015
79Inventor score
Top patents by PatentIndex Score
6 records- 0194US9252172B2Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity regionCHOW SENG GUAN·Filed 2011·Granted Feb 2, 2016·34 cites·18 claims
- 0288US8963326B2Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migrationBAO XUSHENG·Filed 2011·Granted Feb 24, 2015·13 cites·24 claims
- 0364US9171769B2Semiconductor device and method of forming openings through encapsulant to reduce warpage and stress on semiconductor packageCHOW SENG GUAN·Filed 2010·Granted Oct 27, 2015·2 cites·21 claims
- 0463US9397058B2Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migrationSTATS CHIPPAC LTD·Filed 2014·Granted Jul 19, 2016·1 cites·25 claims
- 0557US9142522B2Semiconductor device and method of forming RDL under bump for electrical connection to enclosed bumpBAO XUSHENG·Filed 2011·Granted Sep 22, 2015·1 cites·19 claims
- 0655US9620557B2Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity regionSTATS CHIPPAC LTD·Filed 2015·Granted Apr 11, 2017·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Ma Phoo Pwint Hlaing files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →