Inventor · disambiguated record
Mathew Koshy
Also filed as: KOSHY MATHEW · KOSHY MATHEW P
11 granted patents·152 citations·filing 2006–2017
90Inventor score
Top patents by PatentIndex Score
11 records- 0192US7689948B1System and method for model-based scoring and yield predictionCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Mar 30, 2010·35 cites·20 claims
- 0290US7707528B1System and method for performing verification based upon both rules and modelsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 27, 2010·25 cites·23 claims
- 0388US8146032B2Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designsCHEN QIUSHI·Filed 2009·Granted Mar 27, 2012·37 cites·29 claims
- 0484US9798573B1Physical to virtual scheduling system and methodKOSHY MATHEW P·Filed 2010·Granted Oct 24, 2017·12 cites·20 claims
- 0583US7657856B1Method and system for parallel processing of IC design layoutsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 2, 2010·15 cites·28 claims
- 0680US7886243B1System and method for using rules-based analysis to enhance models-based analysisCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Feb 8, 2011·12 cites·13 claims
- 0770US8522181B2Capacitance extraction for advanced device technologiesNIEUWOUDT ARTHUR·Filed 2012·Granted Aug 27, 2013·4 cites·20 claims
- 0869US7984399B1System and method for random defect yield simulation of chip with built-in redundancyCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jul 19, 2011·5 cites·16 claims
- 0968US8863055B2Capacitance extraction for advanced device technologiesSYNOPSYS INC·Filed 2013·Granted Oct 14, 2014·2 cites·18 claims
- 1065US8448096B1Method and system for parallel processing of IC design layoutsWANG XIAOJUN·Filed 2006·Granted May 21, 2013·5 cites·22 claims
- 1154US10545788B2Physical to virtual scheduling system and methodVMWARE INC·Filed 2017·Granted Jan 28, 2020·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →