Inventor · disambiguated record
Mary P. Kusko
Also filed as: KUSKO MARY · KUSKO MARY P · KUSKO MARY PRILOTSKI
75 granted patents·6 pending applications·354 citations·filing 1999–2021
98Inventor score
Top patents by PatentIndex Score
81 records- 0196US9588177B1Optimizing generation of test configurations for built-in self-testingIBM·Filed 2016·Granted Mar 7, 2017·17 cites·20 claims
- 0294US9552449B1Dynamic fault model generation for diagnostics simulation and pattern generationIBM·Filed 2016·Granted Jan 24, 2017·6 cites·18 claims
- 0394US9404969B1Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad diesCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Aug 2, 2016·25 cites·18 claims
- 0490US10060971B2Adjusting latency in a scan cellIBM·Filed 2016·Granted Aug 28, 2018·4 cites·20 claims
- 0590US6308290B1Look ahead scan chain diagnostic methodIBM·Filed 1999·Granted Oct 23, 2001·80 cites·6 claims
- 0689US12174251B2System testing using partitioned and controlled noiseIBM·Filed 2021·Granted Dec 24, 2024·2 cites·20 claims
- 0789US9852245B2Dynamic fault model generation for diagnostics simulation and pattern generationIBM·Filed 2017·Granted Dec 26, 2017·3 cites·20 claims
- 0887US10024910B2Iterative N-detect based logic diagnostic techniqueIBM·Filed 2016·Granted Jul 17, 2018·3 cites·20 claims
- 0987US9355203B2Shared channel masks in on-product test compression systemIBM·Filed 2014·Granted May 31, 2016·8 cites·8 claims
- 1087US6671838B1Method and apparatus for programmable LBIST channel weightingIBM·Filed 2000·Granted Dec 30, 2003·55 cites·11 claims
- 1184US9110135B2Chip testing with exclusive ORIBM·Filed 2013·Granted Aug 18, 2015·4 cites·13 claims
- 1283US6442720B1Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysisIBM·Filed 1999·Granted Aug 27, 2002·50 cites·14 claims
- 1382US10746794B2Logic built in self test circuitry for use in an integrated circuit with scan chainsIBM·Filed 2016·Granted Aug 18, 2020·2 cites·8 claims
- 1482US10649028B2Logic built in self test circuitry for use in an integrated circuit with scan chainsIBM·Filed 2016·Granted May 12, 2020·2 cites·6 claims
- 1582US10088524B2Logic built in self test circuitry for use in an integrated circuit with scan chainsIBM·Filed 2016·Granted Oct 2, 2018·2 cites·12 claims
- 1682US9923579B2Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitryIBM·Filed 2016·Granted Mar 20, 2018·2 cites·13 claims
- 1779US10018672B2Reducing power requirements and switching during logic built-in-self-test and scan testIBM·Filed 2017·Granted Jul 10, 2018·1 cites·10 claims
- 1878US6728914B2Random path delay testing methodologyCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Apr 27, 2004·22 cites·16 claims
- 1977US9292398B2Design-based weighting for logic built-in self-testIBM·Filed 2013·Granted Mar 22, 2016·4 cites·6 claims
- 2073US9746516B2Collecting diagnostic data from chipsIBM·Filed 2016·Granted Aug 29, 2017·1 cites·4 claims
- 2173US9285423B2Managing chip testing dataIBM·Filed 2013·Granted Mar 15, 2016·2 cites·15 claims
- 2272US9297856B2Implementing MISR compression methods for test time reductionIBM·Filed 2013·Granted Mar 29, 2016·2 cites·9 claims
- 2371US10247776B2Structurally assisted functional test and diagnostics for integrated circuitsIBM·Filed 2017·Granted Apr 2, 2019·1 cites·14 claims
- 2471US10067183B2Portion isolation architecture for chip isolation testIBM·Filed 2016·Granted Sep 4, 2018·2 cites·13 claims
- 2571US7831863B2Method for enhancing the diagnostic accuracy of a VLSI chipIBM·Filed 2007·Granted Nov 9, 2010·5 cites·18 claims
- 2667US8566059B2Insertion of faults in logic model used in simulationDESINENI RAO H·Filed 2009·Granted Oct 22, 2013·4 cites·25 claims
- 2766US10168386B2Scan chain latency reductionIBM·Filed 2017·Granted Jan 1, 2019·1 cites·18 claims
- 2866US9372232B2Collecting diagnostic data from chipsIBM·Filed 2013·Granted Jun 21, 2016·1 cites·4 claims
- 2966US9151800B2Chip testing with exclusive ORIBM·Filed 2013·Granted Oct 6, 2015·1 cites·13 claims
- 3065US10768230B2Built-in device testing of integrated circuitsIBM·Filed 2016·Granted Sep 8, 2020·1 cites·17 claims
- 3164US9378318B2Shared channel masks in on-product test compression systemIBM·Filed 2014·Granted Jun 28, 2016·1 cites·8 claims
- 3263US10254336B2Iterative N-detect based logic diagnostic techniqueIBM·Filed 2018·Granted Apr 9, 2019·0 cites·20 claims
- 3363US6836865B2Method and apparatus for facilitating random pattern testing of logic structuresIBM·Filed 2001·Granted Dec 28, 2004·11 cites·19 claims
- 3462US10739401B2Logic built in self test circuitry for use in an integrated circuit with scan chainsIBM·Filed 2018·Granted Aug 11, 2020·0 cites·12 claims
- 3562US10585142B2Functional diagnostics based on dynamic selection of alternate clockingIBM·Filed 2017·Granted Mar 10, 2020·0 cites·13 claims
- 3662US10545188B2Functional diagnostics based on dynamic selection of alternate clockingIBM·Filed 2017·Granted Jan 28, 2020·0 cites·7 claims
- 3762US10018671B2Reducing power requirements and switching during logic built-in-self-test and scan testIBM·Filed 2017·Granted Jul 10, 2018·0 cites·20 claims
- 3861US12105834B2User privacy for autonomous vehiclesIBM·Filed 2020·Granted Oct 1, 2024·0 cites·3 claims
- 3961US11378623B2Diagnostic enhancement for multiple instances of identical structuresIBM·Filed 2020·Granted Jul 5, 2022·0 cites·18 claims
- 4061US11112854B2Operating pulsed latches on a variable power supplyIBM·Filed 2019·Granted Sep 7, 2021·0 cites·19 claims
- 4161US10930364B2Iterative functional test exerciser reload and executionIBM·Filed 2018·Granted Feb 23, 2021·1 cites·20 claims
- 4261US8176105B2Automated file relocationKUSKO MARY P·Filed 2008·Granted May 8, 2012·2 cites·19 claims
- 4360US10169510B2Dynamic fault model generation for diagnostics simulation and pattern generationIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 4460US9929749B2Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitryIBM·Filed 2017·Granted Mar 27, 2018·0 cites·7 claims
- 4560US9915701B2Bypassing an encoded latch on a chip during a test-pattern scanIBM·Filed 2017·Granted Mar 13, 2018·0 cites·7 claims
- 4660US6314540B1Partitioned pseudo-random logic test for improved manufacturability of semiconductor chipsIBM·Filed 1999·Granted Nov 6, 2001·24 cites·18 claims
- 4759US10527674B2Circuit structures to resolve random testabilityIBM·Filed 2017·Granted Jan 7, 2020·0 cites·10 claims
- 4859US9651616B2Reducing power requirements and switching during logic built-in-self-test and scan testIBM·Filed 2015·Granted May 16, 2017·0 cites·9 claims
- 4958US11112457B2Dynamic weight selection process for logic built-in self testIBM·Filed 2019·Granted Sep 7, 2021·0 cites·18 claims
- 5058US10816599B2Dynamically power noise adaptive automatic test pattern generationIBM·Filed 2019·Granted Oct 27, 2020·0 cites·20 claims
Showing the top 50 of 81 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →