Inventor · disambiguated record
Meng-Chyi Lin
Also filed as: LIN MENG-CHYI
19 granted patents·2 pending applications·257 citations·filing 2002–2022
94Inventor score
Files withSYNTEST TECHNOLOGIES INC11SYNOPSYS TAIWAN CO LTD3SYNOPSYS INC2CHIU HUNG CHUN1SPRINGSOFT INC1
Top patents by PatentIndex Score
21 records- 0194US6954887B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 11, 2005·64 cites·33 claims
- 0293US7007213B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Feb 28, 2006·52 cites·30 claims
- 0391US7191373B2Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniquesSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Mar 13, 2007·48 cites·19 claims
- 0486US7552373B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Jun 23, 2009·36 cites·44 claims
- 0580US8739089B2Systems and methods for increasing debugging visibility of prototyping systemsCHIU HUNG CHUN·Filed 2012·Granted May 27, 2014·9 cites·6 claims
- 0678US9449138B2Prototype and emulation system for multiple custom prototype boardsSYNOPSYS TAIWAN CO LTD·Filed 2014·Granted Sep 20, 2016·4 cites·40 claims
- 0778US7444567B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Oct 28, 2008·17 cites·18 claims
- 0876US9057763B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jun 16, 2015·2 cites·98 claims
- 0976US9026875B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted May 5, 2015·2 cites·55 claims
- 1076US8719762B2Method and apparatus for turning custom prototype boards into co-simulation, co-emulation systemsSYNOPSYS TAIWAN CO LTD·Filed 2012·Granted May 6, 2014·5 cites·6 claims
- 1175US7779323B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Aug 17, 2010·5 cites·21 claims
- 1272US8839179B2Prototype and emulation system for multiple custom prototype boardsSYNOPSYS TAIWAN CO LTD·Filed 2013·Granted Sep 16, 2014·3 cites·17 claims
- 1368US8769359B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jul 1, 2014·1 cites·30 claims
- 1468US7904773B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Mar 8, 2011·4 cites·34 claims
- 1560US7970597B2Event-driven emulation systemSPRINGSOFT INC·Filed 2008·Granted Jun 28, 2011·2 cites·19 claims
- 1659US7721173B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2009·Granted May 18, 2010·3 cites·47 claims
- 1756US12321675B2Incremental compilation for FPGA-based systemsSYNOPSYS INC·Filed 2022·Granted Jun 3, 2025·0 cites·18 claims
- 1854US9384313B2Systems and methods for increasing debugging visibility of prototyping systemsSYNOPSYS INC·Filed 2014·Granted Jul 5, 2016·0 cites·10 claims
- 1953US9696377B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECH INC·Filed 2015·Granted Jul 4, 2017·0 cites·12 claims
- 2038US2008082880A1Method of testing high-speed ic with low-speed ic testerWANG HSIN-PO·Filed 2006·Application pending·0 cites
- 2135US2004153926A1Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuitFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →