Inventor · disambiguated record
Michael Grillberger
Also filed as: GRILLBERGER MICHAEL
13 granted patents·6 pending applications·60 citations·filing 2008–2024
90Inventor score
Files withGRILLBERGER MICHAEL6GLOBALFOUNDRIES INC4HUISINGA TORSTEN2WERNER THOMAS2ADVANCED MICRO DEVICES INC1
Top patents by PatentIndex Score
19 records- 0187US8598714B2Semiconductor device comprising through hole vias having a stress relaxation mechanismHUISINGA TORSTEN·Filed 2010·Granted Dec 3, 2013·11 cites·21 claims
- 0285US8399335B2Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal featuresHUISINGA TORSTEN·Filed 2010·Granted Mar 19, 2013·9 cites·18 claims
- 0381US8497583B2Stress reduction in chip packaging by a stress compensation region formed around the chipCHUMAKOV DMYTRO·Filed 2010·Granted Jul 30, 2013·7 cites·13 claims
- 0478US7982313B2Semiconductor device including stress relaxation gaps for enhancing chip package interaction stabilityADVANCED MICRO DEVICES INC·Filed 2009·Granted Jul 19, 2011·8 cites·21 claims
- 0577US8357610B2Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectricsGLOBALFOUNDRIES INC·Filed 2009·Granted Jan 22, 2013·6 cites·21 claims
- 0676US8479578B2Assessing metal stack integrity in sophisticated semiconductor devices by mechanically stressing die contactsGEISLER HOLM·Filed 2010·Granted Jul 9, 2013·6 cites·28 claims
- 0775US8080866B23-D integrated semiconductor device comprising intermediate heat spreading capabilitiesWERNER THOMAS·Filed 2009·Granted Dec 20, 2011·5 cites·15 claims
- 0867US10014279B2Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilitiesGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 3, 2018·1 cites·20 claims
- 0966US8482123B2Stress reduction in chip packaging by using a low-temperature chip-package connection regimeGRILLBERGER MICHAEL·Filed 2011·Granted Jul 9, 2013·2 cites·23 claims
- 1066US7829357B2Method and test structure for monitoring CMP processes in metallization layers of semiconductor devicesGLOBALFOUNDRIES INC·Filed 2008·Granted Nov 9, 2010·2 cites·17 claims
- 1162US9318468B23-D integrated semiconductor device comprising intermediate heat spreading capabilitiesWERNER THOMAS·Filed 2011·Granted Apr 19, 2016·1 cites·27 claims
- 1259US8920027B2Assessing thermal mechanical characteristics of complex semiconductor devices by integrated heating systemsGRILLBERGER MICHAEL·Filed 2011·Granted Dec 30, 2014·1 cites·15 claims
- 1355US8501545B2Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regimeGRILLBERGER MICHAEL·Filed 2010·Granted Aug 6, 2013·1 cites·21 claims
- 1454US2025279349A1Capacitive junction between conductive line and conductive pillar with methods to form sameGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 1549US2013130498A1Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectricsGLOBALFOUNDRIES INC·Filed 2012·Application pending·0 cites
- 1647US2023402555A1Reflective semiconductor device with mirror elements having two oxide layers over aluminum layer, and related methodGLOBALFOUNDRIES DRESDEN MOD 1·Filed 2022·Application pending·0 cites
- 1747US2010109005A1Semiconductor device comprising a distributed interconnected sensor structure for die internal monitoring purposesGRILLBERGER MICHAEL·Filed 2009·Application pending·0 cites
- 1846US2010252828A1Semiconductor device comprising a chip internal electrical test structure allowing electrical measurements during the fabrication processGRILLBERGER MICHAEL·Filed 2009·Application pending·0 cites
- 1945US2009294921A1Semiconductor device comprising metal lines with a selectively formed dielectric cap layerGRILLBERGER MICHAEL·Filed 2009·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →