Inventor · disambiguated record
Ming Wang Sze
Also filed as: SZE MING WANG
12 granted patents·1 pending application·643 citations·filing 2002–2014
93Inventor score
Top patents by PatentIndex Score
13 records- 0196US6987032B1Ball grid array package and process for manufacturing sameASAT LTD·Filed 2003·Granted Jan 17, 2006·126 cites·29 claims
- 0294US7315080B1Ball grid array package that includes a collapsible spacer for separating die adapter from a heat spreaderASAT LTD·Filed 2004·Granted Jan 1, 2008·76 cites·5 claims
- 0394US6979594B1Process for manufacturing ball grid array packageASAT LTD·Filed 2002·Granted Dec 27, 2005·92 cites·14 claims
- 0494US6737755B1Ball grid array package with improved thermal characteristicsASAT LTD·Filed 2002·Granted May 18, 2004·109 cites·14 claims
- 0593US6818472B1Ball grid array packageASAT LTD·Filed 2003·Granted Nov 16, 2004·69 cites·3 claims
- 0693US6800948B1Ball grid array packageASAT LTD·Filed 2002·Granted Oct 5, 2004·74 cites·6 claims
- 0790US6586834B1Die-up tape ball grid array packageASAT LTD·Filed 2002·Granted Jul 1, 2003·78 cites·8 claims
- 0878US8610262B1Ball grid array package with improved thermal characteristicsMCLELLAN NEIL·Filed 2005·Granted Dec 17, 2013·9 cites·11 claims
- 0974US9390993B2Semiconductor border protection sealantBROADCOM CORP·Filed 2014·Granted Jul 12, 2016·3 cites·31 claims
- 1072US9449903B2Ball grid array package with improved thermal characteristicsUTAC HONG KONG LTD·Filed 2013·Granted Sep 20, 2016·3 cites·7 claims
- 1161US8077439B2Method and system for mitigating risk of electrostatic discharge for a system on chip (SOC)DARABI HOOMAN·Filed 2008·Granted Dec 13, 2011·2 cites·20 claims
- 1258US8193613B2Semiconductor die having increased usable areaWANG KEN JIAN MING·Filed 2007·Granted Jun 5, 2012·2 cites·19 claims
- 1340US2008220206A1Semiconductor die for increasing yield and usable wafer areaWANG KEN JIAN MING·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →