Inventor · disambiguated record
Michael L. Takefman
Also filed as: TAKEFMAN MICHAEL · TAKEFMAN MICHAEL L · TAKEFMAN MICHAEL LEWIS
30 granted patents·10 pending applications·753 citations·filing 1990–2024
96Inventor score
Top patents by PatentIndex Score
40 records- 0198US8738853B2Load reduction dual in-line memory module (LRDIMM) and method for programming the sameDIABLO TECHNOLOGIES INC·Filed 2013·Granted May 27, 2014·67 cites·20 claims
- 0296US8713379B2System and method of interfacing co-processors and input/output devices via a main memory systemTAKEFMAN MICHAEL L·Filed 2011·Granted Apr 29, 2014·80 cites·13 claims
- 0396US8452917B2Load reduction dual in-line memory module (LRDIMM) and method for programming the sameAMER MAHER·Filed 2009·Granted May 28, 2013·64 cites·29 claims
- 0494US8615599B1Method and apparatus for preventing loops in a network by controlling broadcastsTAKEFMAN MICHAEL·Filed 2006·Granted Dec 24, 2013·327 cites·22 claims
- 0591US9552175B2System and method for providing a command buffer in a memory systemDIABLO TECH INC·Filed 2014·Granted Jan 24, 2017·17 cites·32 claims
- 0689US10580465B2System and method for providing a configurable timing control for a memory systemRAMBUS INC·Filed 2018·Granted Mar 3, 2020·7 cites·10 claims
- 0788US9444495B2System and method of interfacing co-processors and input/output devices via a main memory systemDIABLO TECH INC·Filed 2015·Granted Sep 13, 2016·4 cites·37 claims
- 0885US9015408B2Load reduction dual in-line memory module (LRDIMM) and method for programming the sameDIABLO TECHNOLOGIES INC·Filed 2014·Granted Apr 21, 2015·6 cites·20 claims
- 0979US11789662B2System and method of interfacing co-processors and input/output devices via a main memory systemRAMBUS INC·Filed 2022·Granted Oct 17, 2023·0 cites·19 claims
- 1079US11061841B2System and method for implementing a multi-threaded device driver in a computer systemRAMBUS INC·Filed 2020·Granted Jul 13, 2021·1 cites·20 claims
- 1177US10168954B2System and method of interfacing co-processors and input/output devices via a main memory systemRAMBUS INC·Filed 2016·Granted Jan 1, 2019·1 cites·14 claims
- 1274US11422749B2System and method of interfacing co-processors and input/output devices via a main memory systemRAMBUS INC·Filed 2021·Granted Aug 23, 2022·0 cites·20 claims
- 1374US2025117354A1Network transceiver with clock sharing between diesMARVELL ASIA PTE LTD·Filed 2024·Application pending·0 cites
- 1473US5761197ACommunications in a distribution networkNORTHERN TELECOM LTD·Filed 1994·Granted Jun 2, 1998·67 cites·21 claims
- 1572US5285527APredictive historical cache memoryNORTHERN TELECOM LTD·Filed 1990·Granted Feb 8, 1994·70 cites·2 claims
- 1671US10942682B2System and method of interfacing co-processors and input/output devices via a main memory systemRAMBUS INC·Filed 2020·Granted Mar 9, 2021·0 cites·20 claims
- 1771US9449651B2System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipsetDIABLO TECH INC·Filed 2015·Granted Sep 20, 2016·3 cites·20 claims
- 1871US8972805B2System and method of interfacing co-processors and input/output devices via a main memory systemDIABLO TECHNOLOGIES INC·Filed 2014·Granted Mar 3, 2015·1 cites·38 claims
- 1970US11640836B2System and method for providing a configurable timing control for a memory systemRAMBUS INC·Filed 2021·Granted May 2, 2023·0 cites·20 claims
- 2067US12204486B2Network transceiver with clock sharing between diesMARVELL ASIA PTE LTD·Filed 2022·Granted Jan 21, 2025·0 cites·26 claims
- 2166US10725704B2System and method of interfacing co-processors and input/output devices via a main memory systemRAMBUS INC·Filed 2018·Granted Jul 28, 2020·0 cites·20 claims
- 2265US11062743B2System and method for providing a configurable timing control for a memory systemRAMBUS INC·Filed 2020·Granted Jul 13, 2021·0 cites·20 claims
- 2363US9575908B2System and method for unlocking additional functions of a moduleDIABLO TECH INC·Filed 2014·Granted Feb 21, 2017·1 cites·14 claims
- 2459US10719466B2System and method for implementing a multi-threaded device driver in a computer systemRAMBUS INC·Filed 2018·Granted Jul 21, 2020·0 cites·14 claims
- 2559US7453873B1Methods and apparatus for filtering packets for preventing packet reorder and duplication in a networkCISCO TECH INC·Filed 2003·Granted Nov 18, 2008·6 cites·31 claims
- 2658US2025004211A1Error correction and recovery in optical communication systems with low-power optical source devicesMARVELL ASIA PTE LTD·Filed 2024·Application pending·0 cites
- 2756US9465557B2Load reduction dual in-line memory module (LRDIMM) and method for programming the sameDIABLO TECH INC·Filed 2015·Granted Oct 11, 2016·0 cites·20 claims
- 2855US2016041933A1System and method for implementing a multi-threaded device driver in a computer systemDIABLO TECHNOLOGIES INC·Filed 2014·Application pending·0 cites
- 2955US2025156270A1Monitoring fec information in multi-chip environmentMARVELL ASIA PTE LTD·Filed 2024·Application pending·0 cites
- 3053US12375205B1Systems and methods for performance monitoring with forward error correction mechanismMARVELL ASIA PTE LTD·Filed 2023·Granted Jul 29, 2025·0 cites·21 claims
- 3151US9779020B2System and method for providing an address cache for memory map learningDIABLO TECH INC·Filed 2014·Granted Oct 3, 2017·0 cites·20 claims
- 3251US9088484B1Method and apparatus for preventing loops in a network by controlling broadcastsCISCO TECH INC·Filed 2013·Granted Jul 21, 2015·0 cites·20 claims
- 3350US5835036AMethod of encoding data for transmissionCISCO SYSTEMS CO·Filed 1997·Granted Nov 10, 1998·31 cites·17 claims
- 3447US2015347151A1System and method for booting from a non-volatile memoryDIABLO TECHNOLOGIES INC·Filed 2014·Application pending·0 cites
- 3546US2016041917A1System and method for mirroring a volatile memory of a computer systemDIABLO TECHNOLOGIES INC·Filed 2014·Application pending·0 cites
- 3645US2015324281A1System and method of implementing an object storage device on a computer main memory systemDIABLO TECHNOLOGIES INC·Filed 2014·Application pending·0 cites
- 3744US2015326684A1System and method of accessing and controlling a co-processor and/or input/output device via remote direct memory accessDIABLO TECHNOLOGIES INC·Filed 2014·Application pending·0 cites
- 3844US2015310898A1System and method for providing a configurable timing control for a memory systemDIABLO TECHNOLOGIES INC·Filed 2015·Application pending·0 cites
- 3943US7742410B1Methods and apparatus for using gap packets to create a bandwidth buffer over which packets can be sent to reduce or eliminate overflow conditionsCISCO TECH INC·Filed 2002·Granted Jun 22, 2010·0 cites·19 claims
- 4040US2016371204A1System and method for offsetting the data buffer latency of a device implementing a jedec standard ddr-4 lrdimm chipsetDIABLO TECH INC·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →