System and method for providing a configurable timing control for a memory system

Abstract

A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.

What is claimed: 
     
         1 . A system for providing a timing control to a memory module comprising:
 a first interface to receive a DIMM clock and configuration information;   a second interface to a first data bus;   a third interface to a second data bus;   a plurality of flip-flops;   a multiplexor coupled to the plurality of flip-flops;   a first control block for controlling to hold an input data within the plurality of flip-flops;   a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay;   wherein the input data is received via the second interface;   wherein the programmable delay is received via the first interface; and   wherein the output data is sent out with the timing delay via the third interface.   
     
     
         2 . A re-timer circuit comprising:
 a clock generation circuit for receiving a DIMM clock signal and outputting at least one delayed clock signal;   a first delay circuit that receives a first data signal and a first data strobe signal and delays the first data signal by a first programmable delay to produce a delayed first data signal, and generates a first output data strobe, with a defined timing relationship between the first delayed data signal, the first output data strobe signal and the DIMM clock signal.   
     
     
         3 . The re-timer circuit of  claim 2  further comprising:
 a second delay circuit that receives a second data signal and a second data strobe signal and delays the second data signal by a second programmable delay to produce a delayed second data signal, and generates a second output data strobe, with a defined timing relationship between the second delayed data signal, the second output data strobe signal and the DIMM clock signal. 
 
     
     
         4 . The re-timer circuit of  claim 3  wherein:
 the first delay circuit comprises a programmable delay circuit that delays the first data strobe relative to the first data input to produce a first delayed data strobe. 
 
     
     
         5 . The re-timer circuit of  claim 4  wherein:
 the first delay circuit comprises: 
 a plurality of flipflops that are enabled in sequence based on the first delayed data strobe to store respective pairs of bits of the first data signal 
 a multiplexer having inputs coupled to outputs of the plurality of flipflops and having an output that is from selected one of the flipflops; 
 a DQ transmitter coupled to the output of the multiplexer that transmits the first delayed data signal; 
 a DQS transmitter that transmits the first output data strobe. 
 a control circuit that controls the multiplexer, 
 
     
     
         6 . The system of  claim 2  wherein the programmable delay has a range of programmability such that the defined timing relationship is configurable to be compatible with at least one of an RDIMM, an LRDIMM or UDIMM. 
     
     
         7 . A memory module comprising:
 a CPIO (coprocessor or I/O);   a plurality of re-timer circuits according to  claim 2  connecting data outputs of the CPIO to outputs of the memory module.   
     
     
         8 . A memory module comprising:
 a CPIO having a plurality of data outputs;   a plurality of data buffer circuits connecting the data outputs of the CPIO to outputs of the memory module;   the CPIO comprising a respective re-timer circuit according to  claim 2  for each data output.   
     
     
         9 . A memory module comprising:
 a CPIO having a plurality of data outputs connected to outputs of the memory module;   the CPIO comprising a respective re-timer circuit according to  claim 2  for each data output.   
     
     
         10 . A memory module comprising:
 a CPIO having a plurality of data outputs connected to outputs of the memory module;   the CPIO comprising a respective re-timer circuit according to  claim 2  for each data output;   a plurality of re-timer circuits with fixed delay coupling outputs of the CPIO to outputs of the memory module.   
     
     
         11 . A memory module comprising:
 a re-timer circuit according to  claim 2 ;   a DRAM coupled to the re-timer circuit.   
     
     
         12 . A memory module comprising:
 a CPIO having a plurality of data outputs connected to outputs of the memory module;   the CPIO comprising a respective re-timer circuit according to  claim 2  for each data output;   a plurality of re-timer circuits according to  claim 2  coupling outputs of the CPIO to outputs of the memory module.   
     
     
         13 . A buffer comprising:
 a plurality of data paths, each data path comprising:   a respective first DDR PHY connected to a pipeline connected to a respective second DDR PHY   wherein each respective second DDR PHY comprises a re-timer circuit according to  claim 2 .   
     
     
         14 . A method comprising:
 receiving a DIMM clock signal;   based on the DIMM clock signal, outputting at least one delayed clock signal;   receiving a first data signal and a first data strobe signal;   using at least one of the delayed clock signal, delaying the first data signal by a first programmable delay to produce a delayed first data signal and generating a first output data strobe, with a defined timing relationship between the first delayed data signal, the first output data strobe signal and the DIMM clock signal;   transmitting the delayed first data signal and the first output data strobe.   
     
     
         15 . The method of  claim 14  wherein delaying and generating comprise:
 delaying the first data strobe by a programmable delay relative to the first data input to produce a first delayed data strobe; 
 enabling a plurality of flipflops in sequence based on the first delayed data strobe to store respective pairs of bits of the first data signal; 
 multiplexing outputs of the plurality of flipflops wherein the first delayed data signal is based on an output of the multiplexing. 
 
     
     
         16 . The method of  claim 14  wherein the programmable delay has a range of programmability such that the defined timing relationship is configurable to be compatible with at least one of an RDIMM, an LRDIMM or UDIMM. 
     
     
         17 . The method of  claim 14  further comprising receiving at least one configuration parameter, wherein the programmable delay is a function of the received at least one configuration parameter. 
     
     
         18 . The method of  claim 17  further comprising:
 controlling the selection and/or generation of the at least one delayed clock based on the received at least one configuration parameter. 
 
     
     
         19 . The method of  claim 14  further comprising performing the method for each of a plurality of data signals and corresponding data strobe signals with respective programmable delays. 
     
     
         20 . The method of  claim 14  further comprising:
 performing the method with a first programmable delay for a write operation, and performing the method with a second programmable delay for a read operation.